01:38 <memeka> mszyprow: ping

01:39 <memeka> mszyprow: i found why Mali is slow on 5.4 kernel, maybe you can explain the actual cause :P

01:40 <memeka> mszyprow: since it's your commit :D

02:12 <memeka> mszyprow: https://github.com/mihailescu2m/linux/commit/8686764fc0711f409b8fcaaa76e7c5a816e9160b

06:53 <mszyprow> memeka: pong

06:53 <mszyprow> memeka: okay, then G3D needs special parent clock save+restore procedure

06:54 <mszyprow> memeka: otherwise it will get stuct at 24MHz oscilator

06:54 <mszyprow> memeka: -> poor performance

06:54 <mszyprow> memeka: I will try to prepare a patch for testing in a few minutes

06:54 <memeka> mszyprow: mszyprow yes, I already did that before the pd was added

06:55 <memeka> In mali drivers

06:56 <mszyprow> memeka: clock reparenting must be done after every power domain off/on procedure

06:57 <mszyprow> memeka: g3d clocks needs similar fix like baf7b79e1ad79a41fafd8ab8597b9a96962d822d

06:57 <memeka> mszyprow: https://github.com/mihailescu2m/linux/commit/cfa70219eb5a6572a5e26300d382161da1d2038e

06:58 <mszyprow> memeka: the problem is that even if you manually call clk_set_rate, the common clock framework might not update the clk registers which lost its state after power domain off

06:58 <mszyprow> due to regmap proxy in-between

06:59 <memeka> mszyprow: so where should that be done?

07:00 <mszyprow> memeka: drivers/clk/samsung/clk-exynos5420.c, see commit baf7b79e1ad79a41fafd8ab8597b9a96962d822d

07:11 <memeka> mszyprow: thx

07:14 <mszyprow> memeka: I've sent you a patch, please test and let me know if it fixes your issue

07:21 <memeka> mszyprow: thx will do that in a few hours, ooo now

07:22 <memeka> mszyprow: this means that mali driver can now set only mali_clk, and parents will be set automatically right?

07:22 <mszyprow> memeka: right

07:22 <memeka> 👍

07:22 <mszyprow> memeka: parents can be assigned in a standard way in dts (assigned-parent property)

07:23 <memeka> mszyprow: oh I didn’t know :)