lekernel changed the topic of #m-labs to: Mixxeo, Migen, MiSoC & other M-Labs projects :: fka #milkymist :: Logs http://irclog.whitequark.org/m-labs
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<qwebirc90339> I hav implemented a frequency divider using D flip-flop as shown here http://www.electronics-tutorials.ws/counter/count_1.html
<qwebirc90339> i.e connect Qi to D
<qwebirc90339> My code and Verilog code is shown here http://pastebin.com/T27hbAQd
<qwebirc90339> Could anyone let me know if there are any mistakes in my code - i.e testing proceedure etc
<qwebirc90339> Also please let me know if my usage of
<qwebirc90339> Connect = Signal()
<qwebirc90339> for connecting D and Qi is correct
<lekernel> qwebirc90339, Migen (and FPGAs) are for synchronous circuits; this isn't one
<lekernel> well, the first one (and yours) are. but not the others.
<lekernel> 4-bit counter in migen is count = Signal(4); self.sync += count.eq(count + 1)
<lekernel> but that generates a synchronous counter, not a ripple counter
<qwebirc90339> yes. I understood what you said
<qwebirc90339> this is not the right application where Migen should be used
<qwebirc90339> there are easier ways migen can generate a counter(like you have shown)
<qwebirc90339> and not by connecting D flipflops to form a ripple counter
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<qwebirc90339> I have implemented a Johnson counter using my D flip-flops
<qwebirc90339> If you check the code, there are some unused signals. Is there any ways to remove those ?
<qwebirc90339> without modifying my d flip-flop ?
<qwebirc90339> Unwanted/unused parts are marked in the Python and Verilog code
<lekernel> seriously, this is the wrong way to code a Johnson counter in Migen
<lekernel> Q = Signal(3)
<lekernel> self.sync += Q.eq(Cat(Q[1:], ~Q[0]))
<lekernel> or something like that
<qwebirc90339> I think I am totally biased by the Verilog way of coding and never using the powers of python
<lekernel> you can do almost the same in Verilog
<lekernel> reg [2:0] Q;
<lekernel> always @(clk) Q <= {~Q[0], Q[2:1]}
<qwebirc90339> Thanks a lot for the clarification you have provided
<ysionneau> git bisecting rtems is so slow :(
<ysionneau> the bootstrap stuff is guilty about it
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