lekernel changed the topic of #m-labs to: Mixxeo, Migen, MiSoC & other M-Labs projects :: fka #milkymist :: Logs http://irclog.whitequark.org/m-labs
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<rjo> i seem to remember a discussion about a gcc-lm32 bug some time ago. what was that bug about? can i trust my current gcc-lm32?
<sb0> there aren't major bugs in 4.5.x
<sb0> and svn head is mostly functional (after Jon Beniston's patch) but I managed to crash it on code that seems related to floating point
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<sb0> rjo, is there a good reason for keeping both SyncFIFO and SyncFIFORelaxed? or can we have SyncFIFORelaxed only?
<sb0> all modern FPGAs that I know of require registered memories for block-RAM
<GitHub57> [migen] sbourdeauducq pushed 2 new commits to master: http://git.io/akpkZA
<GitHub57> migen/master 9deddbd Robert Jordens: test/test_cordic: fix for new Simulation API
<GitHub57> migen/master 7649028 Robert Jordens: test/support: fix default ncycles
<sb0> on the other hand... for small FIFOs, not using block RAM makes sense
<sb0> maybe SyncFIFO should be a factory function that decides which one to use depending on the depth of the FIFO
<GitHub43> [NetBSD] fallen pushed 1 new commit to master: http://git.io/S-itLA
<GitHub43> NetBSD/master 0cc2475 Yann Sionneau: Fix clock driver: irq mask for irq handler registration was random
<sb0> or... we just accept the logic overhead of using SyncFIFORelaxed at all times, as long as it does not degrade timing for small FIFOs
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