lekernel changed the topic of #m-labs to: Mixxeo, Migen, MiSoC & other M-Labs projects :: fka #milkymist :: Logs http://irclog.whitequark.org/m-labs
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<FabM> yop
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<sb0> hey FabM
<sb0> have you made progress with your board def files?
<FabM> Hy sb0
<FabM> I hope I will find some times in this month to finish it
<ysionneau> sb0: you are using the papilio pro board to test ARTIQ?
<sb0> yes
<sb0> for now
<sb0> not sure yet what board we'll use in the end
<ysionneau> planning on switching to another board in the near future? or waiting for a full custom board to be made?
<sb0> I don't think a full custom board makes a lot of sense. it'll probably be COTS board + FMC add-on
<sb0> maybe kc705
<ysionneau> right ok
<ysionneau> in the mean time I can buy a papilio pro as it's quite inexpensive
<sb0> the gateware should be portable
<ysionneau> kc705 that's another story
<sb0> you can probably run it on the m1
<ysionneau> I guess I would need to tweak the DDR controller setup to match the m1?
<sb0> I think it will run as-is if you build misoc with -Ot cpu_type or1k -p m1
<ysionneau> wow, ok
<sb0> you don't need to use the artiq target
<sb0> there isn't any custom core yet
<ysionneau> ah ok the artiq target is to target the papilio pro but so far it's still "generic"
<ysionneau> so I can just use the m1 target
<sb0> and when there is, you could probably run it on the m1 by using mlabs_video/minisoc as a base
<ysionneau> yes I'm looking at this file right now
<sb0> it's the same as simplesoc, with a gpio on the led and or1k as default cpu
<ysionneau> it seems lasmicon geometry settings are a bit different between papilio pro and m1
<ysionneau> but yes I can use mlabs_video as a base
<sb0> yeah, it's very different sdram
<ysionneau> or just add some if () to use different sdram settings if target is m1 in the artiq file
<sb0> I don't want to maintain artiq on m1...
<ysionneau> ok right
<sb0> I think the easiest route is to inherit from mlabs_video.MiniSoC and add the ARTIQ cores
<ysionneau> shouldn't we put sdram settings in the migen/mibuild/platform files as well?
<sb0> the latter are pretty simple
<ysionneau> so that you can just do -p <some_target> and then voila, it takes the correct sdram stuff
<ysionneau> instead of putting the sdram info in the design, so that the design can be further board agnostic
<sb0> it's not that simple, there are timing settings too and they depend on how the whole design is clocked
<sb0> and what the selected CAS latency is
<sb0> sdram_geom could be platform-supplied, yes
<ysionneau> humm ok
<sb0> re. the ARTIQ cores: there will be a DDS chip driver (https://github.com/m-labs/nist-dds-ttl-tester/blob/master/testerlib/ad9858/__init__.py) and a real-time IO core
<sb0> both are pretty useless on the M1 without the corresponding hardware...
<sb0> and there aren't enough IO pins to run them
<ysionneau> yea sure I understand that in fact it does not make that much sense to support other boards
<ysionneau> except for testing some basic features
<sb0> and really testing those cores requires a mid-range oscilloscope, at least
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<ysionneau> the kind of equipement Electrolab has I guess :)
<sb0> I think so
<ysionneau> I will ask Zenos about what kind of scope they have but it would surprise me if they didn't have a crazy GHz scope
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<ysionneau> so any write to 0-63 will trigger the FSM to forward the write to the DDS chip
<ysionneau> same for read
<ysionneau> wa, read seems to take lots of cycles
<sb0> yeah, that chip interface is primarily made for writing (as explained in its datasheet)
<sb0> reading is for debug purposes
<ysionneau> ok
<ysionneau> you already have samples of the chip? or so far only testing via simulation to see if your core respects the waveforms of the datasheet
<sb0> that chip is already used in some equipment, and there's an adapter for the ppro that connects to it (and the ppro uses this core)
<sb0> ARTIQ is mostly software...
<ysionneau> yes and a bit of gateware glue to speak to the outside world (equipments)
<sb0> the gateware does the fine io timing (via dtc/tdc cores), and real-time control (when a low response time is desired)
<sb0> it also programs some dds chips (the actual dds triggering is via dtc pulses) as it's faster to do it that way
<larsc> so what is artiq?
<sb0> experiment control software/gateware for this: http://www.nist.gov/pml/div688/ions-080812.cfm
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<rjo_> ysionneau: we have loads of those dds on custom backplanes and a adapter for ppro. there is also hard timed gateware: https://github.com/nist-ionstorage/ventilator/tree/master/gateware/ventilator
<rjo_> ysionneau: https://github.com/nist-ionstorage/ventilator/blob/master/gateware/ventilator/wishbone.py e.g. lets you schedule wishbone ops with cycle accuracy.
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