sb0 changed the topic of #m-labs to: ARTIQ, Migen, MiSoC, Mixxeo & other M-Labs projects :: fka #milkymist :: Logs http://irclog.whitequark.org/m-labs
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<GitHub92> [sinara] marmeladapk pushed 1 new commit to master: https://github.com/m-labs/sinara/commit/6314b8cbb26b07efa4a4b0ad9669ee033bf611f3
<GitHub92> sinara/master 6314b8c marmeladapk: Kasli fixes...
<sb0> Arpit: you have to instantiate the FPGA differential buffer (e.g. OBUFTDS) using Instance in Migen
<sb0> for a quick hack you can hardcode that into the SPI core
<sb0> doing this properly and portably is a bit trickier, needs either changing the API of the SPI core to support external buffers, or add another "special" to Migen to support those buffers (there is already support for them but without tristate, https://github.com/m-labs/migen/blob/b730cafbf1fa52b116296bc327d8e3e181f88f11/migen/genlib/io.py#L23)
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<GitHub54> [smoltcp] whitequark commented on issue #44: > A proper implementation would involve actual routing tables, but I propose we adopt this or other limited solution as a stop-gap for now.... https://git.io/v5d1E
<sb0> rjo, how many registers would be required to implement latency compensation with pipelines instead of tweaking timestamps?
<sb0> rjo, and did we agree that user-defined latency compensation by just adding a configurable offset to each channel was useful?
<GitHub75> [artiq] sbourdeauducq commented on issue #40: How about the following:... https://github.com/m-labs/artiq/issues/40#issuecomment-330021573
<GitHub153> [artiq] sbourdeauducq commented on issue #40: How about the following:... https://github.com/m-labs/artiq/issues/40#issuecomment-330021573
<GitHub147> [artiq] sbourdeauducq commented on issue #40: How about the following:... https://github.com/m-labs/artiq/issues/40#issuecomment-330021573
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<GitHub122> [artiq] sbourdeauducq commented on issue #40: How about the following:... https://github.com/m-labs/artiq/issues/40#issuecomment-330021573
<GitHub153> [smoltcp] batonius commented on issue #44: @little-dude It's kinda messy PoC right now, so I haven't been pushing, here it is - https://github.com/batonius/netstack/tree/smolnetd . So far I've implemented the `ip:` scheme enough for `icmpd` and `udpd` to use it and for `dns` and `ping` to work on top of them. `tcpd` is useless for now because it expects the `ip:` scheme to calculate TCP checksum.... https://git.io/v5dH2
<GitHub139> [artiq] hartytp commented on issue #40: I'm not really the right person to ask about that. Try @cjbe or @kilckverbot, or the NIST/ARL guys... https://github.com/m-labs/artiq/issues/40#issuecomment-330027186
<GitHub7> [artiq] hartytp commented on issue #40: I'm not really the right person to ask about that. Try @cjbe or @klickverbot, or the NIST/ARL guys... https://github.com/m-labs/artiq/issues/40#issuecomment-330027186
<sb0> whitequark, what's the status of tcp reassembly? last time you said it was almost finished
<sb0> rjo, anyway I think I found a way to tweak timestamps that would work fine with SED
<GitHub112> [artiq] sbourdeauducq pushed 1 new commit to rtio-sed: https://github.com/m-labs/artiq/commit/65baca8c57a6933eb35f41aa1d6d5ef9c98d6fc9
<GitHub112> artiq/rtio-sed 65baca8 Sebastien Bourdeauducq: rtio: clean up error-prone rtlink.get_or_zero()
<sb0> bb-m-labs, force build --branch=rtio-sed artiq
<bb-m-labs> build forced [ETA 32m50s]
<bb-m-labs> I'll give a shout when the build finishes
<whitequark> sb0: writing tests for edge cases of segment joining
<bb-m-labs> build #774 of artiq-board is complete: Success [build successful] Build details are at http://buildbot.m-labs.hk/builders/artiq-board/builds/774
<bb-m-labs> build #1675 of artiq is complete: Failure [failed python_unittest_2] Build details are at http://buildbot.m-labs.hk/builders/artiq/builds/1675
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<rjo> sb0: about 100 bits * 20 depth registers on average for each SAWG RTIO channel, 18000 FF per SAWG channel.
<rjo> sb0: yes. just one offset would go a long way
<rjo> sb0: good. i start loosing track of SED. for me reading through the discussions each time is becomming erroneous and time consuming. could we pack it up into a design doc?
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<GitHub24> [sinara] gkasprow pushed 2 new commits to master: https://github.com/m-labs/sinara/compare/6314b8cbb26b...7a710f2bee10
<GitHub24> sinara/master 4ed8f39 Greg: fixed issues #308 #307 #294 #309
<GitHub24> sinara/master 7a710f2 Greg: Merge branch 'master' of https://github.com/m-labs/sinara
<rjo> whitequark, sb0: re the crystal for the si5324 on sayma and kasli: is there a special reason that frequency was selected or was it just the one from the kc705?
<rjo> scratch that. they don't specify anything else...
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<GitHub155> [sinara] gkasprow pushed 2 new commits to master: https://github.com/m-labs/sinara/compare/7a710f2bee10...11aebd3a2ee1
<GitHub155> sinara/master ee43099 Greg: fixed #272, reduced pdf size
<GitHub155> sinara/master 11aebd3 Greg: reduced pdf size
<GitHub44> [sinara] gkasprow pushed 2 new commits to master: https://github.com/m-labs/sinara/compare/11aebd3a2ee1...b731f43b93b5
<GitHub44> sinara/master 9e5deb5 Greg: fixed #282, #312, component placement done, routing started
<GitHub44> sinara/master b731f43 Greg: #282 #312 fixed, placement done, routing started
<GitHub109> [sinara] gkasprow pushed 1 new commit to master: https://github.com/m-labs/sinara/commit/8d5e059f597737c2b4b22827634212ac36f48965
<GitHub109> sinara/master 8d5e059 Greg: removed a few BOM lines