00:54 <jbqubit> I have setup with Kasli/v1.0, Urukul/9910/v1.1. Built and flashed kasli_sysu. Urukul is installed on "eem1", "eem0".

00:55 <jbqubit> I can toggle urukul switches, eg urukul0_ch2.sw and see leds flash.

00:55 <jbqubit> self.urukul0_cpld.init() is ok

00:55 <jbqubit> self.urukul0_ch0.init() throws PLL lock timeout

00:57 <jbqubit> I've tried increasing wait time for PLL lock rom 100 ms to 10 s. But still no lock. Any idea what's gone wrong?

01:09 <jbqubit> This was with internal clock for both Kasli and Urukul.

01:11 <jbqubit> When I apply 100 MHz clock to both Kasli and Urukul, -s startup_clock e, specify "refclk": 100e6 for CPLD and "pll_n": 40 for AD9910 I get PLL locking and RF output.

01:27 <GitHub-m-labs> [artiq] sbourdeauducq commented on issue #935: Well @mingshenli does have a Windows machine on which this package is installed, and ``ld`` fails due to missing cygwin1.dll. Interestingly, this only happens when the experiment is run by the master, ``artiq_run`` and ``artiq_compile`` are working correctly. I thought ``ld`` was now completely independent from cygwin? https://github.com/m-labs/artiq/issues/935

01:35 <sb0> rjo, TP-Link MC220L plus fs.com copper cable works. I haven't tried sfp/fiber.

01:41 <GitHub-m-labs> [artiq] sbourdeauducq commented on issue #935: Though that behavior may be due to the ``cygwin1.dll`` he put in the device db directory as a workaround. https://github.com/m-labs/artiq/issues/935#issuecomment-373576782

01:52 <GitHub-m-labs> [artiq] sbourdeauducq commented on issue #935: @mingshenli To double-check: can you activate the artiq conda environment, go to ``d:\artiq1`` and run ``or1k-linux-ld --version``? https://github.com/m-labs/artiq/issues/935#issuecomment-373578614

05:12 <GitHub-m-labs> [artiq] whitequark commented on issue #935: It is completely independent from cygwin. It is compiled as a MinGW application, which means it's windows native. What you're describing seems like the result of master being run from a different conda environment with older binutils package. https://github.com/m-labs/artiq/issues/935#issuecomment-373605441

05:52 <GitHub-m-labs> [artiq] mingshenli commented on issue #935: yes, I find the or1k-linux-ld.exe and run it, but failed because " the cygwin1.ddl can not be found." https://github.com/m-labs/artiq/issues/935#issuecomment-373610830

05:54 <GitHub-m-labs> [artiq] whitequark commented on issue #935: This must be an old conda package. If all else fails, you can remove your entire conda install and start over. https://github.com/m-labs/artiq/issues/935#issuecomment-373611134

06:23 <GitHub-m-labs> [artiq] sbourdeauducq commented on issue #935: @mingshenli did you run it with the current directory being d:\artiq1? where you put cygwin1.dll. https://github.com/m-labs/artiq/issues/935#issuecomment-373615174

06:24 <GitHub-m-labs> [artiq] sbourdeauducq commented on issue #935: @whitequark same conda environment that makes artiq_run work. https://github.com/m-labs/artiq/issues/935#issuecomment-373615296

06:27 <GitHub-m-labs> [artiq] whitequark commented on issue #935: Is there another miniconda installation in PATH? https://github.com/m-labs/artiq/issues/935#issuecomment-373615731

08:13 <GitHub-m-labs> [artiq] mingshenli commented on issue #935: Now it seems work. https://github.com/m-labs/artiq/issues/935#issuecomment-373636354

08:15 <GitHub-m-labs> [artiq] mingshenli commented on issue #935: The cygwin1.dll was at C: where it was install. I create a file in D: and now it seems work. https://github.com/m-labs/artiq/issues/935#issuecomment-373636354

08:18 <GitHub-m-labs> [artiq] mingshenli commented on issue #935: The cygwin1.dll was at C: where it was install. I create a file in D: and now it seems work. (a cmd window flash) https://github.com/m-labs/artiq/issues/935#issuecomment-373636354

08:35 <rjo> jbqubit: nice! if you want to use the XO on urukul, you have to move the capacitor in the clock path.

09:06 <GitHub-m-labs> [artiq] sbourdeauducq commented on issue #935: @mingshenli Still, what is the output of ``or1k-linux-ld --version``? https://github.com/m-labs/artiq/issues/935#issuecomment-373648259

09:13 <bb-m-labs> build #781 of artiq-win64-test is complete: Warnings [warnings python_unittest] Build details are at http://buildbot.m-labs.hk/builders/artiq-win64-test/builds/781 blamelist: whitequark <whitequark@whitequark.org>

09:16 <GitHub-m-labs> [artiq] mingshenli commented on issue #935: nothing happened after I run `start C:\ProgramData\Anaconda3\envs\artiq-3.5\bin\or1k-linux-ld.exe ` except a cmd window flash.... https://github.com/m-labs/artiq/issues/935#issuecomment-373650786

09:17 <bb-m-labs> build #2187 of artiq is complete: Success [build successful] Build details are at http://buildbot.m-labs.hk/builders/artiq/builds/2187

09:18 <GitHub-m-labs> [artiq] sbourdeauducq commented on issue #935: Please follow the instructions carefully:... https://github.com/m-labs/artiq/issues/935#issuecomment-373651138

09:51 <bb-m-labs> build #1353 of artiq-board is complete: Success [build successful] Build details are at http://buildbot.m-labs.hk/builders/artiq-board/builds/1353

10:16 <bb-m-labs> build #782 of artiq-win64-test is complete: Warnings [warnings python_unittest] Build details are at http://buildbot.m-labs.hk/builders/artiq-win64-test/builds/782 blamelist: whitequark <whitequark@whitequark.org>

10:20 <bb-m-labs> build #2188 of artiq is complete: Success [build successful] Build details are at http://buildbot.m-labs.hk/builders/artiq/builds/2188

10:21 <sb0> _florent_, any progress with the sdram?

10:54 <bb-m-labs> build #1354 of artiq-board is complete: Success [build successful] Build details are at http://buildbot.m-labs.hk/builders/artiq-board/builds/1354

11:19 <bb-m-labs> build #783 of artiq-win64-test is complete: Warnings [warnings python_unittest] Build details are at http://buildbot.m-labs.hk/builders/artiq-win64-test/builds/783 blamelist: whitequark <whitequark@whitequark.org>

11:23 <bb-m-labs> build #2189 of artiq is complete: Success [build successful] Build details are at http://buildbot.m-labs.hk/builders/artiq/builds/2189

12:16 <GitHub-m-labs> [artiq] mingshenli commented on issue #935: do as follow?... https://github.com/m-labs/artiq/issues/935#issuecomment-373695937

12:44 <GitHub-m-labs> [artiq] sbourdeauducq commented on issue #935: Yes. https://github.com/m-labs/artiq/issues/935#issuecomment-373702151

12:46 <GitHub-m-labs> [artiq] mingshenli commented on issue #935: but it didn't work because 'or1k-linux-ld --version' is not a command or file https://github.com/m-labs/artiq/issues/935#issuecomment-373702502

12:47 <GitHub-m-labs> [artiq] sbourdeauducq commented on issue #935: Strange, if you see this screenshot it works:... https://github.com/m-labs/artiq/issues/935#issuecomment-373702902

12:50 <GitHub-m-labs> [artiq] mingshenli commented on issue #935: is it have any influence on running `artiq_run` or other command uploading the python file to the kc-705 board? https://github.com/m-labs/artiq/issues/935#issuecomment-373703626

12:53 <hartytp> rjo: TechnoSystem are now out of Kasli v1.1

12:53 <hartytp> do you know of any more plans to order a batch?

12:54 <hartytp> We're like some more fairly soon (e.g. before finalizing plans for an analog PLL for the CDR)

13:00 <sb0> oh, those things go fast! I might need another two for mainland China labs soon-ish....

13:12 <hartytp> sb0: well, we should start thinking about coordinating another batch

13:51 <rjo> hartytp: not in the next ~month. but thanks for asking!

13:52 <hartytp> ack

13:53 <hartytp> new revision with any fixes, or the same?

13:53 <hartytp> would like some delivered in 6-8weeks

13:53 <rjo> yb+ quadrupole clock transition with kasli and urukul: https://raw.githubusercontent.com/jordens/sandbox/master/Screenshot%20from%202018-03-16%2014-31-11.png

13:54 <rjo> hartytp: definitely add a fan. maybe better xtal, add i2c reset to fpga.. maybe something else. will think about it.

13:55 <hartytp> ack

13:55 <hartytp> that all sounds good (would be nice if we can make gateware on v1.1 and v1.2 compatible so we don't need to build too many versions!)

13:55 <hartytp> can we aim to finalize changes in the next couple of weeks?

13:56 <rjo> ... and maybe the si5326 instead of the si5324

13:56 <rjo> hartytp: yes.

13:56 <rjo> hartytp: should be fpga pin-compatible.

13:57 <hartytp> sounds good

13:59 <sb0> with the fixes we have I'm not sure if the 5326 will bring much to the table... and then we'd have to support both in firmware

21:01 <jbqubit> rjo: Thanks. C103

21:06 <_florent_> sb0: no progress yet on the sdram, i was working on another project. I received the board from hartytp, i'll work on it on monday.