00:03 <TD-Linux> afaik the "normal" zynq way to do DMA is to use a DMA IP on the fpga side, like the Xilinx AXI Stream DMA IP

00:47 <Astro-> it can access the DDR RAM, so that sounds plausible.

00:47 <Astro-> still, programmed I/O is easier to test

00:48 <Astro-> thanks for making me reread :)

08:28 <mtrbot-ml> [mattermost] <sb10q> @astro migen-axi should handle many of the things for you already. it might just need refreshing to the latest misoc api

08:28 <mtrbot-ml> [mattermost] <sb10q> though Alain has made changes recently that may have fixed it already