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<Eldra>
rjo: In my ARTIQ system I want to use an external clock at 100MHz. Since the default clock is the internal from the Si5324 at 125MHz I need to change my device_db.py to keep the time resolution at 1 ns.
<Eldra>
I encounter a problem when I change the ref_multiplier parameter of the CORE class (from 8 to 10).
<Eldra>
In the SPIMaster class their is a test : "assert.ref_period_mu == self.core.ref_multiplier" and the test fail.
<Eldra>
In fact : self. ref_period_mu = self.core.seconds_to_mu(self.coarse_ref_period)
<Eldra>
The problem is : (1e-9*8)//1e-9 gives 8.0 which is the default configuration. But (1e-9*10)//1e-9 gives 9.0 instead of 10. So I would suggest to change the seconds_to_mu() function to use floor() instead of the "//" operator.
<rjo>
I suspect you are confused. Rounding is probably irrelevant for what you want to do.
<rjo>
What do you want do? Reference clock where? Please describe it in detail.
<rjo>
What's "CORE" supposed to be?
<rjo>
Could you post the exact change to the device_db template?
<rjo>
> I need to change my device_db.py to keep the time resolution at 1 ns.
<rjo>
That doesn't make sense to me.
<rjo>
Eldra: All three femto systems already expect an external 100 MHz reference clock. I don't understand what you are trying to do.
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<mtrbot-ml>
[mattermost] <sb10q> Eldra: that's not how it works, the correct way is to set up the si5324 to make 125 from 100
<mtrbot-ml>
[mattermost] <sb10q> You can't have arbitrary ref_multiplier. For stock kasli gateware only 1 and 8 are supported
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<Eldra>
rjo: I need a 100MHz external clock but ARTIQ use its internal clock as frequency reference. If you look in the device_db the core device use a 125MHz frequency. And if I try to remove the external clock after the boot, ARTIQ is still running. Now I try have use "artiq_coremgmt config write -s rtio_clock e" and "artiq_flash start". Sinci I have
<Eldra>
done this, ARTIQ use the external clock as frequency reference.
<Eldra>
The problem is : I need to tell that the frequency is no longer 125 MHz but 100 MHz. To do it I change the device_db.py (especially the core device and the urukul).
<Eldra>
mtrbot-ml: But I want to use a MASER as a clock which, I think, is more stable than the Si5324
<mtrbot-ml>
[mattermost] <sb10q> Eldra: on kasli, external rtio clock bypasses the si5324. this should indeed result in lower noise; but then you cannot have 1ns fine timestamps anymore, they become 1.25ns
<mtrbot-ml>
[mattermost] <sb10q> (when using 100MHz as input)
<mtrbot-ml>
[mattermost] <sb10q> note that those fine timestamps are generated by the FPGA PLL, if noise is very important to you, you should take it into account as well
<Eldra>
mtrbot-ml: But there is a variable in the CORE class called ref_multiplier which, I guess, multiplier the clock to have a 1 GHz. It's default value is 8 (8*125MHz = 1GHz). Now I want to setup this variable at 10 (10*100MHz = 1GHz)
<mtrbot-ml>
[mattermost] <sb10q> 10 is not supported, as I said the only implemented values on kasli are 1 and 8
<mtrbot-ml>
[mattermost] <sb10q> and for switching to 1, you need to disconnect the RTIO PLL as well, which isn't as simple as just changing that value
<Eldra>
So I cannot change pll_n ?
<mtrbot-ml>
[mattermost] <sb10q> pll_n is on Urukul I believe and not what I am talking about
<Eldra>
Sorry... I can change pll_n (in urukul). I mean ref_mulitplier
<mtrbot-ml>
[mattermost] <sb10q> yes, ref_multiplier is more difficult to change
<Eldra>
Difficult or impossible ?
<mtrbot-ml>
[mattermost] <sb10q> setting to 1 is relatively straightforward if you know some FPGA programming, setting to 10 while keeping the same ARTIQ APIs is very hard
<mtrbot-ml>
[mattermost] <sb10q> do you have an issue with the 1.25ns timestamp resolution?
<mtrbot-ml>
[mattermost] <sb10q> or with the FPGA PLL noise?
<Eldra>
I agree that 0.25ns is not a lot but if I can change to still have the 1ns I would be happy to learn how to do it.
<mtrbot-ml>
[mattermost] <sb10q> look at how ttl_serdes_7series works
<rjo>
Eldra: All three femto systems use 100 MHz external clock already. What you are doing is something completely different (external bypass clocking). Just undo your change.
<Eldra>
rjo: They need the 100 MHz to boot. But after they don't use it. I have try to generate a 300MHz sinus with a DDS. When I disconnect the external clock the signal is the same.
<mtrbot-ml>
[mattermost] <sb10q> they still use it afterwards, if you try to reconfigure the dds after 100MHz is disconnected it will not work
<Eldra>
After run "artiq_coremgmt config write -s rtio_clock e" and "artiq_flash start". The 300MHz moved to 240MHz
<Eldra>
And the DDS multiple the signal from the urukul by 32. So the urukul gives 31.25MHz to the DDS. The urukul dives by 4 the signal from the Kasli. Which means the Kasli gives 125MHz and not 100MHz
<Eldra>
But maybe I missunderstood something.
<Eldra>
(And when I read the sysclk of the DDS I have 1GHz)
<mtrbot-ml>
[mattermost] <sb10q> yes the si5324 does 100 -> 125
<mtrbot-ml>
[mattermost] <sb10q> and it tracks the 100 reference
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<Eldra>
I see, But the Si5324 can still work even if it lose the external reference
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<mtrbot-ml>
[mattermost] <sb10q> probably doesn't work well...
<Eldra>
Ok and I have a question about the phase noise. We have a MASER in the lab (which will be use as external clock).
<Eldra>
Because the Si5324 generate the 125MHz, it will be the limitation for the phase noise.
<Eldra>
Is their some code in ARTIQ which fix it N?
<mtrbot-ml>
[mattermost] <sb10q> where is it a problem? you can also clock the dds separately, that's also supported
<Eldra>
Yes that's true. Well thank you for your answer and sorry for my missunderstanding
<Eldra>
If you allow me one more question : I have a Sampler card with LTC2320-16 ADCs. I have no choice to use the Si5324 clock for them right ?
<rjo>
Eldra: The si5324 is unlikely to be a limitation. You should go through the numbers before claiming that.
<rjo>
Sampler is clocked from the FPGA on Kasli. And unless you are using SU-Servo, the sampling is typically not periodic.
<Eldra>
Ok thank you.
<Eldra>
It is write : "SU Servo can for example be used to implement intensity stabilization of laser beams with an amplifier and AOM driven by Urukul and a photodetector connected to Sampler."This is exactly what I want to do.
<Eldra>
I just want to be sure to understand where the clock come from.
<rjo>
As I said. That's SU-Servo. Read up on it.
<_whitenotifier-c>
[smoltcp] whitequark commented on pull request #341: Specify concrete type for Bound::Unbounded - https://git.io/JfRB5
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