<kenaan>
fijal arm64 230e2b6a0bae /rpython/jit/backend/aarch64/: use only first 16 registers and make sure the jitframe_fixed_size agrees
<kenaan>
fijal arm64 0b7c212b0618 /rpython/jit/backend/aarch64/: bring it more to reality
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<arigato>
so the arm (not arm64 so far) backend has got a problem
<arigato>
when it calls make_sure_var_in_reg(v)
<arigato>
if v is a ConstXxx, then it will allocate a register and load the register with the constant value
<arigato>
but this register allocation is not tracked
<arigato>
so the next make_sure_var_in_reg() could very well overwrite it
<arigato>
in the case we're seeing right now, it's the next get_scratch_reg(), which returns the same register
<arigato>
by chance
<mattip>
is this a real-world case on armv8 or does it happen because of the chroot?
<mattip>
we didn't see this on armv7 AFAIK
<arigato>
that's absolutely real-world
<arigato>
OK maybe I'm very wrong, need to dig more
<arigato>
no, I'm wrong I think
<arigato>
sorry
<arigato>
no, I'm right
<arigato>
llsupport.regalloc.return_constant is overridden in arm.regalloc
<arigato>
it's a very bad idea
<arigato>
I have no clue at all how it worked so far
<kenaan>
fijal arm64 4f3f6fe5df0a /rpython/jit/backend/: a bit of progresss. now the same test fails, but for better reasons
<fijal>
yay, maybe realloc_frame is mostly working
<arigato>
ah no, I see now
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<arigato>
pff the whole logic is kind of broken
<arigato>
fijal: please make sure not to copy make_sure_var_in_reg() and return_constant() from arm/regalloc.py
<arigato>
pick another source for these, like ppc/regalloc.py
<arigato>
particularly get_scratch_reg()
<fijal>
arigato: I think I already did
<fijal>
make_sure_var_in_reg at least
<fijal>
hm no wait
<fijal>
it's from llmodel directly
<fijal>
why does arm have its own copy?
<arigato>
the problem is self.temp_boxes
<fijal>
no it does not
<fijal>
arigato: what are you talking about?
<fijal>
make_sure_var_in_reg is just a dispatch to the right regalloc
<arigato>
look for example in ppc/regalloc.py:
<arigato>
it contains only two calls to make_sure_var_in_reg(), in both cases by passing forbidden_vars=self.temp_boxes
<fijal>
I copied all of that
<fijal>
return_constant too
<arigato>
let me finish please
<fijal>
sure
<fijal>
x86 is different though - contains far more calls to make_sure_var_in_reg
<arigato>
arm/regalloc.py contains probably more subtle bugs like the one I'm tracking, and the reason is:
<arigato>
it calls make_sure_var_in_reg from a lot of places, generally not passing forbidden_vars=self.temp_boxes
<fijal>
right, but you have to explain to me why x86 is ok
<arigato>
there is no self.temp_boxes in x86
<fijal>
why is there on arm?
<arigato>
arm introduced get_scratch_reg(), which was not really needed on x86
<fijal>
to get a temporary loc?
<arigato>
yes
<fijal>
we have quite careful handling of temporary locs in x86
<fijal>
which was also a source of some bugs
<arigato>
sure, but now it works
<arigato>
unlike arm
<fijal>
right
<fijal>
so should I kill the whole handling of temp_boxes?
<fijal>
because the "general" solution does not work completely
<arigato>
so just to make sure we're on the same page:
<arigato>
if a prepare_xxx() function calls make_sure_var_in_reg two times, but the first time (only) it's with a ConstInt
<arigato>
the first time it will go through get_scratch_reg()
<arigato>
and the second time it will go to the regular logic in make_sure_var_in_reg()
<fijal>
and the second one does not pass the right thing, yes
<arigato>
but without self.temp_boxes in forbiddenvars
<fijal>
I remember bugs like that in x86
<arigato>
so this particular issue comes from the fact that make_sure_var_in_reg on x86 means "load variable in register, but if it's a constant, don't put it in a register at all"
<arigato>
however on arm it means "really really load a register"
<fijal>
right because we can't use constants in most circumstances
<arigato>
(because of the return_constant() override)
<arigato>
yes
<fijal>
right
<fijal>
ok
<fijal>
I don't have to say "make_sure_var_in_reg allocating something and assigning it to temp boxes is a terrible idea"
<fijal>
now, why on arm64 we can't use one of the spare registers?
<fijal>
seems much saner
<arigato>
yes
<fijal>
because we might need an arbitrary amount of those?
<arigato>
who knows? I think not
* fijal
lunch
<fijal>
let me know how do you resolve it and what do you want me to do on arm64
<fijal>
I think my next problem is that frame_realloc is not called where it should be (I think)
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<kenaan>
arigo default a243e4e0b21c /rpython/jit/backend/: An attempt to find a general fix for arm/regalloc. In this backend (and not the others as far as I can tell), ther...
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