10:47 <lkcl> folks we (Libre-SOC) would very much like to put in a skywater shuttle. what however is preventing us from doing so is the existence of the Caravel GPIO and the Management core.

10:48 <lkcl> thanks to Staf Verhaegen we have access to a full Libre-Licensed IOPads Cell Library (which we can't deploy or test because the Caravel GPIO is in the way)

10:49 <lkcl> we've funding to develop a prototype equivalent for the Caravel GPIO and also a comprehensive "Pin Multiplexer"

10:49 <lkcl> which we can't deploy or test because Caravel GPIO is in the way

10:49 <lkcl> is there anything that can be done about this?

10:53 <lkcl> Coriolis2 is also capable of generating the full IO Ring, if we know where the pad positions are.

10:53 <lkcl> can that be published so that ASICs such as ours can do the entire P&R?

10:54 <lkcl> about the only thing that would be useful to us would be the PLL, although we also have help from Sorbonne University to create a Voltage-Controlled PLL so if the Skywater 130nm PLL cannot be provided as a Cell we have options there, too.

10:59 <lkcl> https://fosdem.org/2021/schedule/event/alliance/

19:44 <mkk_> [Troy Benjegerdes, skywater-pdk] is there a libre-soc irc channel to discuss this further?

20:50 <lkcl> Troy: freenode #libre-soc

20:50 <lkcl> (thanks!)

20:52 <lkcl> if we end up missing due to afk or timezones the logs are at https://libre-soc.org/irclog/