clifford changed the topic of #yosys to: Yosys Open SYnthesis Suite: http://www.clifford.at/yosys/ -- Channel Logs: https://irclog.whitequark.org/yosys
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<ArunINT> Hello everyone!
<daveshah> Hi!
<ArunINT> I have an issue with yosys where vivado compatible verilog i.e (synthesizable in vivado) is throwing "ERROR: Unsupported expression on dynamic range select on signal `$mem2bits$\tlwr_data_buf$test.v" :1086$6'!
<ArunINT> is this the right place to ask this question
<daveshah> Yes, let's see the problematic file
<ArunINT> I cannot share the file as it is NDA bound, but I can try to reproduce this in an example meanwhile here are the details
<ArunINT> reg [63:0] tlwr_data[2:0]; reg [511:0] tlwr_data_buf[2:0]; reg [2:0] tlwr_burst_cntr[2:0]; tlwr_data[idx] = tlwr_data_buf[idx][{tlwr_burst_cntr[idx], 6'h00} +:64];
<ArunINT> idx here is the variable getting incremented in a for loop
<daveshah> I think that is valid Verilog, so this is a bug
<daveshah> I don't know the frontend well enough to fix it, so unless someone else here comes along the best bet is to turn that into a minimal example (the problem seems to be an indexing within a part-select) and create a GitHub issue
<ArunINT> Okay I'll create a github issue, thank you
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