clifford changed the topic of #yosys to: Yosys Open SYnthesis Suite: http://www.clifford.at/yosys/ -- Channel Logs: https://irclog.whitequark.org/yosys
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<jophish1> Hi all
<jophish1> I have some generated systemverilog code and yosys doesn't seem to like it very much
<jophish1> on `function`
<jophish1> Specifically: `.build/clash/HDMITop.topEntity/hdmi_types.sv:44: ERROR: syntax error, unexpected TOK_FUNCTION`
<jophish1> I don't know enough about SV to really be able to tell where the issue is
<FL4SHK> jophish1: you're using SV with yosys? Really?
<jophish1> oh, is this not a cool thing to do?
<FL4SHK> try sv2v if you want to use SV with yosys
<FL4SHK> yosys's SV support is very poor
<jophish1> I was using it because I have SV assertions set up
<FL4SHK> ah
<FL4SHK> that's valid
<FL4SHK> if you're just using assertions, yosys is actually still limited, but it does support enough of that to get the job done
<jophish1> although they're generated too, so I could probably set up a Verilog backend for them too
<FL4SHK> I'm building something intended for use with yosys for formal
<FL4SHK> it's a DSL to generate a VHDL AST
<FL4SHK> combined with the GHDL synthesis plugin, this should handle my needs in a language
<jophish1> hehe, I had no end of trouble using GHDL for this!
<jophish1> Worked first time! Thanks yosys :)
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