ChanServ changed the topic of #linux-rockchip to: Rockchip development discussion | Wiki at http://linux-rockchip.info | Logs at http://irclog.whitequark.org/linux-rockchip | ML at http://groups.google.com/group/linux-rockchip
<naobsd> hmmm what's ARMv8 Crypto Extensions?
<naobsd> Error: selected processor does not support `aese v0.16b,v2.16b'
<naobsd> :(
<naobsd> gcc -march needs +crypto, but I guess rk3368 doesn't support it
<naobsd> lets disable CE support in .config...
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<naobsd> oh well
<naobsd> Features: fp asimd evtstrm aes pmull sha1 sha2 crc32
<naobsd> in /proc/cpuinfo
<naobsd> so it should be supported...?
<naobsd> btw arch/arm64/kernel/asm-offsets.s compile error is not in next-20151208
<naobsd> but there are many commits between 1208..1209
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<naobsd> about armv8 crypto
<naobsd> CFLAGS_aes-ce-cipher.o += -march=armv8-a+crypto
<naobsd> hmm why my compiler failed...
<naobsd> test.c is compilable and no crash
<naobsd> -march=armv8-a+crypto should be ok...
<naobsd> http://pastebin.com/ztvuMZHd +crypto is defined but failed :(
<naobsd> it seems -mgeneral-regs-only disables +crypto...
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<naobsd> next-20151208 is almost fine on both arm(firefly) and arm64(orion r68)
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<xming_> mmind00: 64GB sdxc boots fine too with increased strength
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<mmind00> xming_: \o/ great
<xming_> mmind00: do you have any clues how to get full 4GB?
<mmind00> xming_: uboot is definitly not my thing ... I'm even lacking behind trying to actually test mainline uboot
<sjoerd> mmind00: pfff :)
<mmind00> sjoerd: :-P
<sjoerd> xming_: given the u-boot code for memory setup came from coreboot probably best to check there how it handles boards with different memory sizes
<sjoerd> or at least i assume there are rk chromebooks with 4G
<xming_> sjoerd: you told me try changing dtb, so it's uboot's dtb?
<xming_> I only have to look uboot related right? Not kernel stuggs
<xming_> /stuggs/stuffs
<sjoerd> Right, if u-boot setups and recognize 4G it should adjust the dtb as passed to the kernel with the right memory size
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<xming_> google says Asus C201 uses rk3288 and has 4GB option
<xming_> c201
<sjoerd> Right so i'd look at its coreboot code and see what it does compared with u-boot
<sjoerd> I really don't know the memory setup section too well either and i don't have documentation for the phy which makes everyting a bit limited to, check what known working code does :)
<xming_> so libreboot is the x86 style BIOS/UEFI hacked with emmc/nand support?
<xming_> forked from coreboot?
<sjoerd> hrm?
<sjoerd> No chromeos uses coreboot
<sjoerd> which is why i'm pointing at that
<sjoerd> i'm not sure about libreboot tbh
<xming_> Libreboot was established as a distribution of coreboot without proprietary binary blobs
<xming_> c201 is supported in libreboot, I think I need that
<xming_> without blob init stuffs
<sjoerd> feel free to look at that, whatever gives you the answers really
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<naobsd> what happen if we use ddr blob with mainline u-boot
<naobsd> with proper "load from mask rom" support
<sjoerd> naobsd: things get quite confused
<sjoerd> the ddr blob sets up stuff differently
<sjoerd> I tried that and then u-boot thought there was only 64M ram
<sjoerd> no clue why
<xming_> what a weird tree
<naobsd> rockchip,sdram-channel = /bits/ 8 <0x1 0xa 0x3 0x2 0x1 0x0 0xf 0xf>;
<naobsd> this should be 1GB
<naobsd> I'm not sure this values are not changed or updated while probing
<naobsd> well
<xming_> ah coreboot look much better
<naobsd> ddr blob tells those values, but I cannot refer it for now...
<sjoerd> naobsd: right 1G, 2 channels
<naobsd> so rockchip,sdram-channel should be modified for 4GB
<sjoerd> no 2G
<naobsd> I cannot find any code which updates those values
<sjoerd> 4G ram is 2x2G
<xming_> does firely use DDR3 or LPDDR?
<naobsd> what I said is, those values need to be updated as 2GB for 4GB board
<sjoerd> right
<naobsd> DDR blob prints right values on boot
<naobsd> I don't have it for now
<naobsd> col might be +1
<xming_> blobk uboot output
<xming_> ah missed the lines before
<xming_> Channel a: DDR3 200MHz
<xming_> Bus Width=32 Col=10 Bank=8 Row=15 CS=2 Die Bus-Width=16 Size=2048MB
<xming_> Channel b: DDR3 200MHz
<xming_> Bus Width=32 Col=10 Bank=8 Row=15 CS=2 Die Bus-Width=16 Size=2048MB
<naobsd> CS value is different but I'm not sure which one in rockchip,sdram-channel
<xming_> does the 2GB version also use 2 channels?
<naobsd> rank?
<xming_> only CS is different
<xming_> CS == counts ?
<sjoerd> worth bumping rank to 2 to see if that does the right thing indeed
<sjoerd> you select chips from diffrent ranks using CS (chip select)
<sjoerd> would be interesting to know how the blob figures that kind of stuff out though
<naobsd> http://git.jp.linux-rockchip.org/?p=rk3288_r-box_android4.4.2_sdk.git;a=blob;f=kernel/arch/arm/mach-rockchip/ddr_rk32.c;h=8420e407ce519f3ca55e60122f14bd24bbf93f96;hb=HEAD#l806
<naobsd> http://git.denx.de/?p=u-boot.git;a=blob;f=arch/arm/include/asm/arch-rockchip/ddr_rk3288.h;h=fccabcd2c03e30baf38ce2292ad5a43d883e52f8;hb=HEAD#l469
<naobsd> I assume ram info on pmu reg is compatible
<naobsd> READ_CS_INFO(ch) ((((pPMU_Reg->PMU_PMU_SYS_REG[2])>>(11+(ch)*16))&0x1)+1)
<naobsd> SYS_REG_RANK_SHIFT(ch) (11 + (ch) * 16)
<naobsd> same ddr blob can be used for both 2GB board and 4GB board, it should bedetected at run time
<sjoerd> naobsd: oh intersting, i didn't know the code was available
<naobsd> ddr code is available in RK 3.0/3.10 kernel tree
<xming_> http://git.denx.de/?p=u-boot.git;a=blob;f=arch/arm/mach-rockchip/rk3288/sdram_rk3288.c;h=09017ccf5e634142e0e77a3b2b7b3d9f8bf0e7d8;hb=HEAD#l448
<xming_> can I try
<xming_> rank = sdram_params->ch[channel].rank | 2;
<naobsd> rockchip,sdram-channel = /bits/ 8 <0x2 0xa 0x3 0x2 0x1 0x0 0xf 0xf>;
<naobsd> oh well
<naobsd> "| 1" !?
<naobsd> then 0x2 becomes 3...
<naobsd> rank = 2;
<naobsd> "| 2" is not good if you use sdram-channel = /bits/ 8 <0x1 ...
<naobsd> I recommend "rank = 2;" for now
<naobsd> ah, if all code refers rank as like as "if (rank > 1)" then 3 is ok ;)
<naobsd> oops, there are several "rank | 1"
<xming_> so, should I change the dtb to 'rockchip,sdram-channel = /bits/ 8 <0x2 0xa 0x3 0x2 0x1 0x0 0xf 0xf>'
<xming_> or change the code to 'rank = 2;'
<naobsd> probably it's not so simple
<xming_> as long as it doesn't brick my firefly I don't mind to try
<naobsd> well
<naobsd> sure
<naobsd> it's complicated for me
<xming_> it's almost gibberish to me
<naobsd> all I can do is just try ;)
<xming_> okay
<naobsd> ah
<naobsd> http://git.denx.de/?p=u-boot.git;a=blob;f=arch/arm/mach-rockchip/rk3288/sdram_rk3288.c;h=09017ccf5e634142e0e77a3b2b7b3d9f8bf0e7d8;hb=HEAD#l649
<naobsd> it seems rank is bitmap, not value
<naobsd> so
<naobsd> rockchip,sdram-channel = /bits/ 8 <0x2 0xa 0x3 0x2 0x1 0x0 0xf 0xf>;
<naobsd> and code unchanged ("rank | 1" -> 3) might work
<naobsd> http://git.denx.de/?p=u-boot.git;a=blob;f=arch/arm/mach-rockchip/rk3288/sdram_rk3288.c;h=09017ccf5e634142e0e77a3b2b7b3d9f8bf0e7d8;hb=HEAD#l628 rank is "3" in this case
<xming_> 650 * CS0, n=1
<xming_> 651 * CS1, n=2
<xming_> 652 * CS0 & CS1, n = 3
<xming_> looks promising
<naobsd> cryptic
<naobsd> melt my brain
<xming_> Model: Firefly-RK3288
<xming_> DRAM: 0 Bytes
<xming_> haha
<naobsd> haha
<naobsd> 4GiB is 0 of course
<naobsd> ah sorry unit is MiB in code
<naobsd> something didn't work properly with rank 2 ;)
<naobsd> oh wait
<naobsd> priv->info.size = sdram_size_mb(priv->pmu) << 20;
<naobsd> arch/arm/include/asm/types.h:typedef unsigned long phys_addr_t;
<naobsd> haha
* xming_ waits for the clue :p
<naobsd> mmm
<naobsd> size_mb = min(size_mb, 0xff000000 >> 20);
<naobsd> sdram_size_mb() should return 4GiB-16MiB ?
<naobsd> well
<naobsd> (4GiB - 16MiB) >> 20
<naobsd> then "priv->info.size = sdram_size_mb(priv->pmu) << 20;" should be fine :(
<naobsd> confusing...
<naobsd> well melted brain here
<xming_> :(
<naobsd> zzz
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<xming_> that part is straight from coreboot
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<naobsd> hmmmmmm
<naobsd> need more investigation :(
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<xming_> blah I need the google's fork of coreboot, not the original one
<xming_> still not getting those SoCs
<xming_> finally found them
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<naobsd> I think
<naobsd> ./arch/arm/cpu/armv7/sunxi/dram_sun6i.c ./arch/arm/include/asm/arch-sunxi/dram_sun6i.h should be read
<naobsd> ah maybe netbsd code just read result of configuration...
<naobsd> sun6i sunxi_dram_init() try
<naobsd> well
<naobsd> arch/arm/cpu/armv7/sunxi/dram_helpers.c::mctl_mem_matches()
<naobsd> mmm
<naobsd> saopdfj;owharg
<naobsd> haduhlgaer
<naobsd> yo ho, yo ho,
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<naobsd> hmm, dram common registers in sun6i is no relation to us... :(
<naobsd> ctl/phy should be same
<naobsd> coreboot pistachio code is very straightforward
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<xming_> chromos' coreboot fork has various veyron* platform
<xming_> which is rk3288
<xming_> most codes are very similar to uboot
<xming_> I am following the trail DRAM_SIZE_MB, but can't see that they do much with it
<naobsd> sun6i runtime detection code is interesting
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<amstan> xming_: you want firmware-veyron-6588.B
<xming_> amstan: is that different than the code in git?
<amstan> xming_: you can also ask jwerner over in #chromiumos for more details, he's been the main maintainer of that branch
<amstan> that's the branch that you want
<xming_> amstan: ah thanks for the tip
<amstan> of wait.. you're looking at upstream coreboot?
<xming_> no chromeos'
<amstan> that's what yo uwant
<xming_> yeah I figured that out
<xming_> thanks a lot
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