01:35 <forksand> meh CarlFK i checked spacing on Trellis, not ULX3S. 1 sec

01:38 <forksand> CarlFK: in kicad file it says minimum track size is 0.127mm.

11:47 <kbeckmann> Hi! Just want to say that LiteX is a very cool project and it's fun and easy to use and bring up.

11:48 <kbeckmann> Got curious about nMigen, will it be ported to nMigen in the future or will it stay written in Migen?

15:29 <somlo> _florent_: I suspect commit #ba264418 broke my ability to build: https://pastebin.com/9WS80Fj3

15:31 <somlo> I'm not sure, maybe there's some cmdline flag that's now mandatory that I'm missing?

15:42 <daveshah> somlo: the escaped quotes around serial here don't look righr

15:42 <daveshah> https://github.com/enjoy-digital/litex/commit/ba26441889ee0b24743eb55f32c74daab246555e#diff-5b5aa398d41ddd6086fbe51e97931f5cR545

15:42 <tpb> Title: integration/soc_core: expose more SoC parameters · enjoy-digital/litex@ba26441 · GitHub (at github.com)

15:42 <daveshah> What happens if you do --uart-name serial (which shouldn't add the quotes)

16:25 <somlo> daveshah, _florent_: explicitly adding --uart-name serial seems to work

16:25 <daveshah> somlo: then I think the escaped quotes in the default value string need to be removed

16:27 <somlo> https://pastebin.com/n8LnYMGh

16:28 <somlo> I don't know if you or I should send a PR, or maybe _florent_ can just fix that when he gets to catch up with his IRC log :)

16:32 <somlo> daveshah: thanks for tracking that down, in the mean time my build is cooking again :)

17:20 <keesj> my fomu arrived \o/

19:36 <y2kbugger> Working on adding iceFUN board to litex-buildenv. No problems with gateware+bios+none using lm32 softcpu on harware, but when switching to vexriscv, I can't even hit bios over serial. Tim suggested that wishbone-tool might be a starting point for debugging. I seem to be able to peek with it but the results seem inconsistant. Any help or suggestions

19:36 <y2kbugger> on what to try next would be great.

19:58 <_florent_> kbeckmann: thanks for the feedback, for nMigen, we'll have to evaluate the pros and cons, for now the actual codebase does not have enough unit-tests to be able to do the switch easily, so i'm trying first to improve that and simplify things. Some of the LiteX features/tools also heavily rely on Migen internals, and i haven't evaluated how much rewrite needs to be done to be able to have the similar features/tools

19:58 <_florent_> with nMigen. At least, it will be possible to have Migen/nMigen modules cohabitate in the same LiteX SoC design. (nMigen modules could be elaborated during the build automatically and reintegrated as Migen verilog instances).

20:00 <_florent_> somlo, daveshah: i'm looking at the --uart-name issue

20:06 <_florent_> daveshah: i've been able to get SerDes TX/RX working on ECP5 today (using whitequark's pcie work as a basis), the open-source toolchain is really a time saver for this kind of work! (iterations in a few seconds vs minutes when i was doing similar work for Xilinx).

20:06 <_florent_> https://github.com/enjoy-digital/liteiclink/blob/master/liteiclink/transceiver/serdes_ecp5.py

20:06 <tpb> Title: liteiclink/serdes_ecp5.py at master · enjoy-digital/liteiclink · GitHub (at github.com)

20:06 <daveshah> _florent_: awesome

20:06 <daveshah> Please do say if you hit any bugs

20:07 <_florent_> https://github.com/enjoy-digital/liteiclink/blob/master/examples/transceiver/versa_ecp5.py

20:07 <tpb> Title: liteiclink/versa_ecp5.py at master · enjoy-digital/liteiclink · GitHub (at github.com)

20:07 <_florent_> the design just send K28.5 + a slow counter

20:08 <_florent_> and then on RX we align things and output the counter the leds

20:08 <_florent_> i'll do more tests tomorrow against a Xilinx device

20:10 <_florent_> daveshah: i was using both Diamond and trellis, but haven't had issues with trellis for now

20:10 <daveshah> Hehe, I think that was first SERDES design I tested