13:37 <ysionneau> whaa, OpenRISC guys have ported Debian on or1k http://lists.opencores.org/pipermail/openrisc/2014-January/001565.html

13:37 <ysionneau> amazing

13:37 <ysionneau> so much work

21:25 <GitHub186> [migen] sbourdeauducq pushed 1 new commit to master: http://git.io/ZJJLwg

21:25 <GitHub186> migen/master 63c1d7e Sebastien Bourdeauducq: New simulation API

21:27 <lekernel> ysionneau, it's rather frustrating that all this work is pretty unusable due to the sluggishness of openrisc

21:36 <lekernel> http://www.eetimes.com/document.asp?doc_id=1319754 you could run misoc on the 4K version, including MMU :)

21:36 <lekernel> (http://lists.opencores.org/pipermail/openrisc/2013-October/001455.html)

21:36 <lekernel> except there's no SDRAM

21:37 <lekernel> and last time I checked the lattice software was buggier than ISE

21:45 <lekernel> "hard coded I2C, SPI, and timer/counter blocks" that's one of the stupidest FPGA features ever

22:03 <mumptai> if they are really hardcoded, there is a at least one design feeling stupid now ...

22:04 <ysionneau> lekernel: hey I two of these boards :)

22:04 <ysionneau> I got*

22:04 <ysionneau> but never tried anything with them so far

22:06 <mumptai> a spi to wishboen bridge seems okay though, but a bit slugish performance-wise

22:11 <ysionneau> lekernel: they have several pipeline implementations, maybe the situation has evolved since you last evaluated the openrisc implementation

22:13 <ysionneau> mork1x mor1kx for instance has 3 different pipeline implementations

22:13 <ysionneau> called "capuccino", "espresso" and "prontoespresso"

22:18 <ysionneau> it has mmu, with hardware tlb reload

22:18 <ysionneau> support for it in linux

22:28 <ysionneau> lekernel: is the openrisc that slow? what are its weak points precisely?

22:34 <ysionneau> going to sleep, gn8!