lekernel changed the topic of #m-labs to: Mixxeo, Migen, MiSoC & other M-Labs projects :: fka #milkymist :: Logs http://irclog.whitequark.org/m-labs
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<sb0__> I take it back. I wasn't using setjmp() correctly.
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<GitHub46> [ARTIQ] sbourdeauducq pushed 6 new commits to master: http://git.io/GJg8Ww
<GitHub46> ARTIQ/master ec7a929 Sebastien Bourdeauducq: soc/runtime: provide exception handling services
<GitHub46> ARTIQ/master a8df170 Sebastien Bourdeauducq: py2llvm: support raise statement
<GitHub46> ARTIQ/master b37ceb3 Sebastien Bourdeauducq: soc/runtime: fix use of setjmp
<sb0__> whee! we can throw exceptions from the device
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<mithro> have you guys had any experience with Lattice products?
<sb0__> the fpgas?
<mithro> sb0__: yeah
<sb0__> tried their software one... worse than ISE... gave up
<sb0__> *once
<mithro> sb0__: yeah, that is my understanding of most people's experiances
<mithro> sb0__: you guys generally use Altium for your designs right?
<sb0__> the m1 and mixxeo mainboards are designed with altium, yes
<sb0__> I don't like altium very much, but kicad and geda are worse...
<sb0__> the kicad UI is full of frustrating contradictions
<sb0__> I don't know how much of that mess the CERN folks have cleaned up lately
<mithro> sb0__: Last time I used Altium, it also had quite a few frustrating contradictions and similar problems. I feel like it's pretty much common to any software which has "CAD" in it's name :/
<sb0__> yeah, altium is not perfect - that and it's proprietary, windows, and bloated
<sb0__> have you tried http://circuits.io ?
<sb0__> unfortunately full of startup/cloud/maker BS and recently bought by autodesk, but it looks interesting
<sb0__> (the interface does)
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<GitHub172> [migen] sbourdeauducq pushed 1 new commit to master: http://git.io/sla7ew
<GitHub172> migen/master 967b73b Florent Kermarrec: actorlib/structuring: add reverse parameter to Unpack and Pack
<sb0_> _florent_, how about removing the 'payload' subrecord completely, instead of hiding it with a getattr hack?
<GitHub143> [migen] sbourdeauducq pushed 1 new commit to master: http://git.io/QR7DdQ
<GitHub143> migen/master 66054af Florent Kermarrec: flow/actor: add packetized parameter for Sink and Source
<sb0_> also, what are the actors that cannot be used with the connect method? eventually, what the DFG does is use the same connect method...
<_florent_> hi
<_florent_> just for info, there is an error on the last patch: eop is DIR_S_TO_M too, sorry for that
<_florent_> payload can be removed, for some operation we will just have to do the distinction between the stb, ack, sop, eop and the others signals that are the payload.
<sb0_> ok, can you send new patches?
<_florent_> about the payload? if so, yes I will work on that
<sb0_> yes, and eop direction
<sb0_> hu, why add this Pipeline module? g = DataFlowGraph(), g.add_pipeline(m1, ... mn) does it
<sb0_> maybe we can get rid of the CompositeActor and e.g. make DataFlowGraph (or its replacement) a module itself...
<_florent_> I don't like the fact that the DataFlowGraph add the modules to the submodules, and that AutoCSR do not work on modules in the DataFlowGraph
<GitHub104> [migen] sbourdeauducq pushed 1 new commit to master: http://git.io/emsHhA
<GitHub104> migen/master a03570c Florent Kermarrec: flow/actor: fix eop direction
<_florent_> yes if DataFlowGraph is a module we won't have this behaviour
<sb0_> yeah. and we can add a 'noprefix' feature to the csr mechanism so that the name of the DFG does not appear
<_florent_> yes and thus DataFlowGraph will only connect modules and eventually insert plumbing, etc...
<sb0_> alternatively, we can make DFG not add non-abstract submodules to itself, and only connect them
<sb0_> but then it's easy to forget to add some actor you passed to DFG to the submodules, and it's more 'boilerplate' code
<_florent_> yes but the rules is the same than for the others modules, if you have in mind that DFG does only the connection you will not forget it
<_florent_> I have to go, I'll try to look at that soon, bye
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