lekernel changed the topic of #m-labs to: Mixxeo, Migen, MiSoC & other M-Labs projects :: fka #milkymist :: Logs http://irclog.whitequark.org/m-labs
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<sb0>
already one small thing to hate about kintex7: the flash clock needs to be accessed using a special STARTUPE2 primitive that ise does not insert automatically when trying to use the pin as regular IO
<GitHub123>
[migen] sbourdeauducq pushed 1 new commit to master: http://git.io/601nQA
<sb0>
_florent_, hi. I checked the RESET# pin on the DDR3 - and LVCMOS15 is correct, it's part of the DDR3 standard (so that the SDRAM can be held in reset when Vref is not stable yet)
<sb0>
_florent_, also, platform-dependent mishaps like the STARTUPE2 should not be put in cores
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<sb0>
_florent_, are you able to reconfigure the kc705 from xc3sprog after flashing?
<sb0>
with "xc3sprog -c jtaghs1 -R" I get "Device does not support reconfiguration."
<sb0>
also, the flashing doesn't seem to work here, even though xc3sprog says the verification succeeds. DONE does not go high, and when loading the bitstream manually the BIOS does not boot.
<sb0>
ah, DONE goes high... just takes a long time - much slower than with the preloaded designs
<sb0>
BIOS still broken
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<_florent_>
hi
<_florent_>
I've tested the BIOS on my board, it was working
<_florent_>
but what I'm not sure is that the dummy parameter on my board still has its default value
<_florent_>
maybe you should try with dummy=15
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<_florent_>
in fact the configuration I tested: flashing the BIOS and loading the bistream XC3SPROG
<sb0>
meh, nevermind, I was using the wrong serial port
<_florent_>
:)
<sb0>
ttyUSBx naming is a mess
<_florent_>
ok so on your board the dummy=11 configuration also works?
<sb0>
I disabled XIP and just memory-mapped the SPI flash core to test. it's reading correct data with dummy=11.
<sb0>
recompiling with XIP...
<sb0>
also, after a while, DONE does go high and the board boots from the flash
<sb0>
I guess there's some bitgen option to make the FPGA read the flash faster ...
<_florent_>
yes it's probably reading the flash in FAST_READ mode (1 dq) and not in QIOFR mode (4 dq)
<_florent_>
Where do you want to put the STARTUPE2?
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<sb0>
I put it into the SoC toplevel
<sb0>
I also fixed the addresses
<sb0>
XIP works :)
<GitHub142>
[misoc] sbourdeauducq pushed 1 new commit to master: http://git.io/oyKbxg
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<sb0>
"WARNING:Pack:2949 - The I/O component clk200_p uses an DQS_BIAS attribute with I/O standard LVDS. The DQS_BIAS attribute will be ignored since the selected I/O standard does not support DQS_BIAS usage."
<sb0>
where is that DQS_BIAS attribute coming from?!
<sb0>
hmm, from IBUFDS it seems... and that's totally undocumented... another quirk
<sb0>
"WARNING:PhysDesignRules:2217 - ISERDESE2 instance <ISERDESE2_46> has the attribute INTERFACE_TYPE set to MEMORY and the DATA_RATE to DDR and the DATA_WIDTH to 8. This combination is not recommended. For INTERFACE_TYPE MEMORY and DATA_RATE DDR the recommended DATA_WIDTH values are <4>."
<sb0>
this one is also funny. and no mention anywhere else...
<sb0>
_florent_, I see why you kept the SERDES in NETWORKING mode and used bitslip since it was there :) but I'd rather make overengineering a xilinx-only problem as much as possible, and stay away from bitslip
<sb0>
also this bitslip feature does not make any sense as you can trivially implement it in the fabric using a register and a barrel shifter
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<_florent_>
in fact yes we don't really need bitslip, that was just more convenient to try to find timing but I wasn't aware of the "WARNING:PhysDesignRules:2217
<_florent_>
even if data were not aligned correctly we can still play with CAS, read command phase, read phase
<sb0>
xilinx fpga ios are always full of surprises ;)
<sb0>
yes, totally
<_florent_>
but that's not dynamic
<_florent_>
on the "almost working" timing I provided you, I don't understand why I need to have the IDELAY configured to 27 on the last modules...
<_florent_>
but maybe it was a "WARNING:PhysDesignRules:2217" related issue...
<_florent_>
if you change the INTERFACE_TYPE you will then gain a full sys_clk on read latency
<sb0>
yeah, I tried that and in addition to the warning, the serdes seems to sample the data earlier (only the last 64 bits are SDRAM data)
<sb0>
er, no, last 256
<_florent_>
with INTERFACE_TYPE configured to NETWORKING?
<sb0>
with INTERFACE_TYPE=MEMORY. when you set it to NETWORKING, data is correctly aligned with the SERDES sampling window (all at CAS latency 7)
<sb0>
*last 128
<_florent_>
strange, I was expecting to have the same alignment but only 1 full sys_clk before...
<sb0>
yeah, same. maybe that's what the warning is about
<_florent_>
you can increase the read phase by 1sys4x clk, and read the ouput of the serdes 1 sys_clk after
<_florent_>
but then you loose the 1 sys_clk gain of latency
<_florent_>
btw, I think we should automatically compute read/write cmd phases and read/write phases
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