lekernel changed the topic of #m-labs to: Mixxeo, Migen, MiSoC & other M-Labs projects :: fka #milkymist :: Logs http://irclog.whitequark.org/m-labs
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<sb0> what's the expected state of DM during DDR3 write leveling? don't care?
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<vdmo> hello .. grig from vjunion here ;)
<sb0> hi
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<sb0> those ddr3 sodimm modules seem to have a lot of skew... more than 1ns of dqs/clk timing variation across all bytes
<mumptai> wasn't that one of the things the ddr interfaces have been designed to allow for to make stuff cheaper?
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<GitHub91> [misoc] sbourdeauducq pushed 2 new commits to master: http://git.io/Lk1FqQ
<GitHub91> misoc/master 5483b37 Sebastien Bourdeauducq: k7ddrphy: write leveling and read calibration support
<GitHub91> misoc/master 19abe2b Sebastien Bourdeauducq: k7ddrphy: do not register T at SERDES (fixes timing problem)
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