<_florent_>
I'm working for a customer on a design with an AD9361 chip
<_florent_>
larsc: it seems you worked on the driver & HDL
<_florent_>
if so, I'm reusing in my design the PHY provided by AD: axi_ad9361_dev_if.v
<_florent_>
but I'm not able to find in the driver the function that calibrate the IDELAYE2 on the PHY by the delay_YYY interface
<_florent_>
Do you know this part of the design and/or have some advices on that?
<larsc>
I think we calibrate on the ad9361 side
<larsc>
it's basically run the PR sequence for all possible delay settings
<larsc>
usually you get a continuous area where it works and then the middle of that is choosen
<_florent_>
ah ok, yes I saw that the calibration was done on the ad9361 in the code
<_florent_>
so in fact the IDELAYE2 are not really used?
<larsc>
probably not
<larsc>
as far as I know
<_florent_>
ok :), thanks a lot for that!
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<larsc>
I can ask the HDL guy once he is awake
<_florent_>
yes it will be cool, but I think you are right because I wasn't able to find anything relative to that on the driver
<larsc>
I didn't even knew we had those delay elements on the fpga side until now. But I only have to look into things when they brake and calibration worked fine so far ;)
<_florent_>
ok :), it seems the calibration if the digital interface is done in ad9361_dig_tune and I see the loop to configure and check the calibration on the ad9361 side
<larsc>
yes
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<GitHub176>
[ARTIQ] sbourdeauducq pushed 3 new commits to master: http://git.io/5ardXA
<GitHub176>
ARTIQ/master 4de670b Sebastien Bourdeauducq: examples/dds_test: use integer as boolean (now supported by compiler)
<GitHub176>
ARTIQ/master 76cef04 Sebastien Bourdeauducq: compiler/ir: introduce Fraction type (incomplete)