01:24 <mithro> rjo: If I recall correctly, you were looking at having migen/misoc generate a module hierarchy in the output verilog? I'm very interested in doing something like that so I can get better resource utilization reports (in hierarchical) form from ISE.

07:18 <mithro> rjo: Ahh - I found it -> https://github.com/m-labs/migen/issues/70

10:07 <GitHub84> [artiq] sbourdeauducq commented on issue #793: @jordens what is the final clocking plan and DRTIO transceiver speed decision? https://github.com/m-labs/artiq/issues/793#issuecomment-334996060