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<_florent_>
sb0: I haven't tried with drtio with full artiq design, but at least it was tested on sayma_amc
<_florent_>
sb0: I'll implement the multi-lane initialization procedure soon
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<sb0_>
G33KatWork, without the data mask pins, you're going to need read-modify-write cycles to the DRAM to access with less than full burst granularity
<sb0_>
no impact on reads
<sb0_>
and that's intrinsic to the DRAM interface, the controller cannot do anything about it
<sb0_>
G33KatWork, if your "memory mapped interface" includes a write-back cache with a line length >= the dram burst length, then you don't need the DM.
<sb0_>
(>= and multiple of)
<G33KatWork>
yeah, I was looking for an easy way to test my RAM on that board with easy memory writes from my processor, because I had to reverse engineer the pinout. Without an AXI interface generated by the MIG that's still possible of course, but more work ;)
<G33KatWork>
I thought that maybe litedram generally doesn't use the DM pins and always does full burst writes and all the infrastructure for a whishbone interface which abstracts all that away is alrady there
<G33KatWork>
and litedram looks way simpler than the stuff the MIG generates
<sb0_>
for an even simpler controller there is minicon in misoc
<sb0_>
you can just strip out the DM stuff from it and from the PHY
<sb0_>
then make sure you always use the full burst (i.e. no use of wishbone sel signals on minicon)
<sb0_>
removing DM is very simple, those pins aren't use for anything else
<G33KatWork>
awesome, thanks. I'll check it out
<sb0_>
then use the cache module to connect to another wishbone bus. then you can use sel on the interface to the cache module.
<GitHub96>
[artiq] sbourdeauducq commented on issue #861: This is at initialization, though we don't know at the moment if the link is reliable afterwards when the initialization succeeds. The boards are hot and I don't know if it happens with a cold board. What @enjoy-digital was suggesting you check is whether the HMC830 outputs clean clocks or not. https://github.com/m-labs/artiq/issues/861#issuecomment-348691456
<sb0_>
whitequark, how is ethernet?
<GitHub136>
[artiq] sbourdeauducq commented on issue #861: My understanding of the HMC830 is that if the PLL unlocks, it will not automatically try to relock or it will do so only once (depending on a bit in a configuration register). https://github.com/m-labs/artiq/issues/861#issuecomment-348693873
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<FelixVi>
Is the 4 x Ad9912 version of Urukul currently available?