<GitHub35>
sinara/master c6d0bec Paweł: Kasli - small improvements in routing for PI...
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<shuffle2>
grumble, even the example project using axi in vivado just hangs :( must be linux doing something dumb
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<shuffle2>
also tried exporting all fclk to userspace and enabling them at 50mhz...still hangs :(
<GitHub89>
[smoltcp] pothos commented on pull request #65 700ddd0: Ah, yes. Then by just looking at the two numbers there is no way to distinguish between the case of normal operation with local_seq_no just wrapped before the max statement and the retransmission case. There is also a wrapped case for retransmission where the minimum would have to be taken. So first a way to find out if the value of remote_last_seq was coming from a retransmission is need
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<GitHub49>
[artiq] sbourdeauducq commented on issue #687: Zotino done including monitoring. For Novo there now is a generic driver for shift registers that can be used for the PGIA. Talking to the main ADC chip still needs to be done. https://github.com/m-labs/artiq/issues/687#issuecomment-341312399
<GitHub93>
[artiq] sbourdeauducq commented on issue #687: Zotino done including monitoring. For Novo there is now is a generic driver for shift registers that can be used for the PGIA. Talking to the main ADC chip still needs to be done. https://github.com/m-labs/artiq/issues/687#issuecomment-341312399
<sb0>
_florent_, does your media converter find the ethernet carrier from sayma? this is borked here for some reason
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<sb0>
ordering new cables and media converters...sigh
<shuffle2>
hm, so...axi works totally as expected...when not using linux :(
<shuffle2>
added some debug stuff and using xilinx' xmd thing. works fine D:<
<shuffle2>
is there a better thing to do than just dumping lots of config mmio space and comparing against linux? ugh
<GitHub141>
[smoltcp] pothos commented on issue #65: This is roughly how I would solve it now. Instead of the casts it could use PartialOrd::partial_cmp.... https://git.io/vFsEg
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<cr1901_modern>
Is there any particular reason why there is no "DifferentialIO" (which would instantiate IOBUFDS) in genlib.io?
<cr1901_modern>
My guess is that AsyncResetSynchronizer is less common than MultiReg, so one can afford a tight constraint like that
<rjo>
cr1901_modern: they are both common.
<rjo>
cr1901_modern: may very well also benefit from that constraint. do you want to educate yourself on that topic and crosscheck the available info with what we do in migen?
<cr1901_modern>
rjo: Sure... let me finish my current patch for migen and I'll spend some time reading
<shuffle2>
finally! https://www.xilinx.com/support/answers/58615.html axi from linux works :D (i had seen this before, but in the context i saw it, the people said it had already been fixed in xdevcfg driver...)
<_florent_>
sb0: haven't really try ethernet with the media converter, i'll try while working on amc/rtm
<shuffle2>
lol...now re-writing the bitstream is broken, though. even if i undo those level shifter changes.
<shuffle2>
also, vivado axi sample works, while simple csr test w/migen does not :(
<shuffle2>
(reads return 0, writes cause bus error)
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<rjo>
_florent_, sb0: that `dw` parameter in the liteeth phy/mac interface does not work for any dw > 8, right? the eop.eq(sink.last_be) won't work correctly AFAICT.
<shuffle2>
ok actually read and writes do work on migen CSRs. it's just that each 32bit arm access only maps to 1 axi slave byte. bus error happens on writes if top 24bits are nonzero
<shuffle2>
which is kind of expected i guess?
<whitequark>
I think so yes
<cr1901_modern>
shuffle2: "it's just that each 32bit arm access only maps to 1 axi slave byte" That is expected- well Idk if the bus error part is. But it's how the CSR bus is designed.
<cr1901_modern>
A more "dense" decoding scheme is more annoying to impl and you have 256MB of addr space for CSR
<larsc>
on altera the axi bridge only has 2M
<shuffle2>
oh hah. the bus error was just because __attribute__((packed)) was causing gcc to emit weird non-32bit accesses (even though the struct members were word-aligned and marked volatile...)
<whitequark>
this is a common issue with packed and bitfields
<shuffle2>
sure, no bitfields tho, just u32s
<larsc>
does the compiler assume that packed is not aligned?
<shuffle2>
yea seems so (adding aligned(4) on the struct fixes it)
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<npisenti_>
I had a quick question about the FSM module
<npisenti_>
In the generated verilog code, the always @(*) block begins with assigning a <= 1'd0
<npisenti_>
so unless I explicitly have a `self.a.eq(...)` for each state in the FSM, i'll get that default assignment
<npisenti_>
maybe i'm missing something (or that is just good coding practice anyways), but i naively assumed that `reg a` would hold it's value unless getting another explicit assignment
<npisenti_>
(feels a bit silly to include `self.a.eq(self.a)` in the other states
<rjo>
always @(*) blocks are effectively combinatorial. the only register you can affect with a FSM directly (within act()) is the FSM state. for other things use .ingoing() or {after,before}_{leaving,entering}()
<rjo>
*ongoing()
<rjo>
(hi npisenti_)
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<npisenti>
i see... alternatively to latch a value into reg a, I could use NextValue? or is taht really intended for, eg, running a counter within a particular FSM state?
<rjo>
yes. that's correct. although i suspect NextValue() may change or move or disappear in the future.
<sb0>
well it could be generalized to all comb blocks. or suppress the notion of sync/comb block and use nextvalue (or equivalent) for registers.