sb0 changed the topic of #m-labs to: ARTIQ, Migen, MiSoC, Mixxeo & other M-Labs projects :: fka #milkymist :: Logs http://irclog.whitequark.org/m-labs
<GitHub102> [sinara] gkasprow pushed 1 new commit to master: https://git.io/vbUFD
<GitHub102> sinara/master e39a48b Greg: Novo v1.2 panel update...
<GitHub183> [artiq] sbourdeauducq commented on issue #857: There will be a 3.1 release soon that includes the fix. Do you confirm that the problem is fixed in 4.0.dev? https://github.com/m-labs/artiq/issues/857#issuecomment-347730067
<sb0> whitequark, any progress on the ethernet switch fix?
<sb0> also can we have a smoltcp release with the ARP bug fixed?
FelixVi has quit []
rohitksingh_work has joined #m-labs
ohama has quit [Ping timeout: 240 seconds]
ohama has joined #m-labs
<sb0> _florent_, does Gearbox really have to define new clock domains?
<sb0> you're doing that for a domain with the reset being the OR of the two resets
<sb0> I see only two options:
<sb0> 1. this reset needs another ResetSynchronizer, or
<sb0> 2. resets in the original domains are already well-behaved and defining new domains is not necessary
<sb0> but maybe I'm wrong... could be better to add some explanations in the comments in any case
<sb0> why not use the same synchronization mechanism used in s6ddrphy?
<sb0> has this Gearbox been tested with non-integer ratios? seems a bit fragile ...
sb0 has quit [Quit: Leaving]
sb0 has joined #m-labs
<sb0> _florent_, how about this type of design?
sb0 has quit [Client Quit]
sb0 has joined #m-labs
<sb0> when building for sayma
<bb-m-labs> build #289 of misoc is complete: Success [build successful] Build details are at http://buildbot.m-labs.hk/builders/misoc/builds/289
<sb0> I wonder how xilinx manages to mess up everything like this https://www.xilinx.com/support/answers/43482.html and https://www.xilinx.com/support/answers/53561.html
<sb0> and with altera being bought by intel, who invent things like ME, SMM and ACPI, there is little hope
<larsc> knowing how such large companies work on the inside I'm more supprised that anything works at all
<rjo> sb0: i know. _florent_ wrote that code. either of us three can fix that.
<sb0> I don't know what the solution is - I didn't touch JESD other than moving code around
<sb0> I'm sending 1.2GHz to the sayma now, with the hmc830 bypassed (and the JESD reset commented out), the ad9154 SERDES PLL locks but then I get "no sync lock"
<sb0> _florent_, are you generating sysref?
<sb0> meh that's dumb
<sb0> csr issue...
<sb0> rjo, why did you add ad9154 to the mem_map?
<rjo> did i do that recently? or was that forgotten when the spi busses csrs moved from kernel to comms cpu?
<rjo> if you need the runtime fixed today you'll have to figure it out yourself or ask florent.
<sb0> I fixed it, still get "no sync lock"
<rjo> are you sure that wasn't a left over from phaser when you altered the spi busses there?
<sb0> it's still in the phaser...
<sb0> speaking of the phaser, should we remove it from artiq-4?
<rjo> as i said, iirc you did that move and maybe that was forgotten.
<rjo> dropping phaser when sayma is there is fine with me.
<rjo> i don't see right now why ad9154 should be in mem_map.
<GitHub13> [artiq] sbourdeauducq pushed 1 new commit to release-3: https://github.com/m-labs/artiq/commit/45f510bcdcd2aa8e32f8fd1acadc14c3ce2d7822
<GitHub13> artiq/release-3 45f510b Sebastien Bourdeauducq: phaser: remove ad9154 from mem_map
<bb-m-labs> build #923 of artiq-board is complete: Success [build successful] Build details are at http://buildbot.m-labs.hk/builders/artiq-board/builds/923
<GitHub36> [artiq] sbourdeauducq opened issue #859: serwb initialization is not reliable https://github.com/m-labs/artiq/issues/859
<bb-m-labs> build #1807 of artiq is complete: Failure [failed] Build details are at http://buildbot.m-labs.hk/builders/artiq/builds/1807 blamelist: Sebastien Bourdeauducq <sb@m-labs.hk>
<GitHub167> [artiq] sbourdeauducq opened issue #860: HMC830 fails to lock https://github.com/m-labs/artiq/issues/860
<GitHub135> [artiq] sbourdeauducq closed issue #859: serwb initialization is not reliable https://github.com/m-labs/artiq/issues/859
<_florent_> sb0: here now
<_florent_> sb0: are you using the ad9154.rs I was using?
<sb0> I'm using the one currently in the artiq repos
<_florent_> sb0: let me look at it
<_florent_> sb0: reading the log, but what's your actual issue?
<sb0> _florent_, 1) comments about clock frequencies are confusing (should be div=2)?
<sb0> 2) ad9154 says "no sync lock"
<sb0> 3) hmc830 not locking, serwb not reliable (as I mentioned before)
<whitequark> sb0: you don't need a smoltcp release, just package it with a git url
<sb0> 4) what do you think of the suggested gearbox design?
<whitequark> i.e. cherry-picking that commit is enough
<sb0> whitequark, can we sync smoltcp releases with artiq releases like we do for misoc/migen?
sb0 has quit [Quit: Leaving]
<_florent_> 4) don't seems to be generic. the one i'm using has been tested with various configurations, but yes we can maybe improve the reset part
<whitequark> sb0: I'd rather have it as an independent project, since unlike misoc/migen it's useful (and already used) for more than artiq alone
<whitequark> well that and pointing to a git tag instead of a git hash makes no real difference
<whitequark> we depend on other things from git like compiler_builtins anyway
<_florent_> sb0: i'll look at the others points
sb0 has joined #m-labs
<sb0> _florent_, why is it not generic?
<sb0> whitequark, what is the smoltcp release process?
<sb0> and yes I know about the other git parts and I don't like them too much
<sb0> _florent_, do you actually use the non-integer ratios? other than that, the architecture I'm proposing has the same features as yours, afaict
<sb0> those non-integer ratios seem to require complicated reset conditions...
<GitHub47> [smoltcp] phil-opp commented on issue #75: Thanks for the review! I think I addressed all your comments. https://github.com/m-labs/smoltcp/pull/75#issuecomment-347838936
<whitequark> sb0: releases just have to be free from known bugs and have reasonably complete APIs
<whitequark> I don't want to have a half-working IPv6 implementation there
<sb0> whitequark, yes, that sounds like something we'd want to base artiq releases on
<whitequark> sb0: okay
<sb0> whitequark, and artiq remains the main user and sponsor of smoltcp.
<sb0> misoc/migen is also used in a few other things, by the way
<whitequark> isn't that the litex fork?
<whitequark> precisely because artiq drives misoc/migen development?
<sb0> to put it bluntly, litex exists because _florent_ doesn't want to clean up code
<_florent_> sb0: yes i'm using non integer ratios (8 /10 hdmi), but you don't need non-integer ratio, you can use different code in migen
<sb0> I don't mind non-artiq patches and features into migen/misoc, as long as they're clean
<whitequark> the reason I said that about smoltcp is because of how much code external contributors bring, like I expect that I wouldn't have to actually do much coding
<whitequark> to get an IPv6 stack*
<sb0> _florent_, why does hdmi need that?
<whitequark> sb0: ack re litex
<_florent_> whitequark, sb0: that's not the reason...
<sb0> _florent_, well, you started litex after I removed a bunch of dirty code from migen/misoc
rohitksingh_work has quit [Read error: Connection reset by peer]
<_florent_> sb0: i needed something that was convenient for me to work with and more open (I sometime need iterations to get clean code, i know you don't...)
<whitequark> sb0: regarding eth switch fix, I'm doing some work on artiq_devtool that will let me do gateware modification much more easily
<whitequark> I'll finish it soon, and then will just have to debug the gateware I already wrote
<whitequark> sb0: btw shouldn't we add release-* branches to CI autobuild filter?
<sb0> whitequark, yes, we can add those branches
<whitequark> ok
<sb0> _florent_, but are you willing to do those iterations?
<_florent_> sb0; i was willing to, but you also have to understand that you have to give time to people to do that and explain a bit more what is clean for you
bb-m-labs has quit [Quit: buildmaster reconfigured: bot disconnecting]
<GitHub-m-labs> [buildbot-config] whitequark pushed 1 new commit to master: https://git.io/vbTDP
<GitHub-m-labs> buildbot-config/master ff1e2b5 whitequark: Build changes not just on master branch but also release-\d+ ones.
bb-m-labs has joined #m-labs
<GitHub103> [smoltcp] whitequark pushed 1 new commit to master: https://github.com/m-labs/smoltcp/commit/7727687330d409915572f96de8896cd6747b10ca
<GitHub103> smoltcp/master 7727687 Dan Robertson: Add IPv6 address and cidr to wire...
<sb0> whitequark, the problem though, is the board may or may not be flashed with the latest master...
<sb0> I'm fine with that, but that may be a problem for your workflow
<sb0> _florent_, ok
<whitequark> sb0: I already had issues with that when you invoked manual builds, it is not that much of a problem
<whitequark> besides the new artiq_devtool should simplify things I think
<travis-ci> m-labs/smoltcp#452 (master - 7727687 : Dan Robertson): The build passed.
<GitHub147> [artiq] KaifengC commented on issue #858: The versions of the packaging is checked by comparing `/artiq/conda/artiq-dev/meta.yaml` and `pip list`.... https://github.com/m-labs/artiq/issues/858#issuecomment-347884523
<_florent_> sb0: ad9154.rs is not up to date, i said it was not commited to avoid breaking compatibility with kc705
<_florent_> sb0: that's probably not easy to have a common file, i'll probably create a ad9154_kc705.rs and ad9154_sayma.rs is we need to keep kc705 compatibility
<sb0> _florent_, we don't need to keep kc705 compatibility
<sb0> I don't think it's particularly hard to keep it, but not worth the effort either...
<_florent_> sb0: ok thanks
<sb0> _florent_, what needs to be changed?
<_florent_> jesd parameters, ad9154 lane mapping, spi config, etc...
<_florent_> I'm going to do a test and I'll commit things
<_florent_> with the ad9154.rs you were using, it's normal to get no sync lock
<rjo> sb0: just to check: there was no deliverable of DRTIO-syncing phaser to sayma?
<sb0> rjo, no there wasn't
<rjo> ok. fine with nixing it. i'd announce that.
<sb0> _florent_, btw if JTAG doesn't work on Sayma that's likely because of the flaky 1.8V power supply
<sb0> power cycle the boards with
<sb0> echo > /dev/ttyACM0
<sb0> and wait a few seconds
<_florent_> ok
<sb0> do NOT attempt to use JTAG while the board is powered off, this messes up the FTDI-chip and then it requires the USB cable to be physically unplugged and replugged
<sb0> if you want to change the clock to the saymas, there is a SynthNV on /dev/ttyACM_synthnv
<rjo> sb0: just fyi if anyone digs into that i looked at the schematics around the ftdi and i couldn't find a reason for that behavior. maybe something for alexander as well.
<sb0> but the synthnv firmware is buggy as well, and it's easy to crash it till it requires a physical USB plug cycle ...
<GitHub15> [artiq] enjoy-digital pushed 2 new commits to master: https://github.com/m-labs/artiq/compare/19498e59f9d2...bd75954192d4
<GitHub15> artiq/master 8b8da39 Florent Kermarrec: libboard/hmc830_7043.rs: fix HMC7043 comments
<GitHub15> artiq/master bd75954 Florent Kermarrec: libboard/ad9154: update for sayma (spi, jesd parameters, linerate), breaks kc705/ad9154 fmc support
<rjo> also fyi, there is stub synthnv code in ~rj/synthnv.py. call it like "synthnv.py x1 f300.0 h1 a33 o1 e e"
<bb-m-labs> build #924 of artiq-board is complete: Success [build successful] Build details are at http://buildbot.m-labs.hk/builders/artiq-board/builds/924
<bb-m-labs> build #1808 of artiq is complete: Failure [failed] Build details are at http://buildbot.m-labs.hk/builders/artiq/builds/1808 blamelist: Florent Kermarrec <florent@enjoy-digital.fr>
<GitHub48> [artiq] philipkent commented on issue #850: Thanks, I will try that. https://github.com/m-labs/artiq/issues/850#issuecomment-347952530
mumptai has joined #m-labs
<GitHub18> [artiq] philipkent closed issue #850: Log messages not printed in scheduled experiment https://github.com/m-labs/artiq/issues/850
rjo has quit [Ping timeout: 276 seconds]
rjo has joined #m-labs
mumptai has quit [Remote host closed the connection]