sb0 changed the topic of #m-labs to: ARTIQ, Migen, MiSoC, Mixxeo & other M-Labs projects :: fka #milkymist :: Logs http://irclog.whitequark.org/m-labs
<sb0>
if the range is narrow, which it is and can be justified to avoid locking to multiples, then locking means as much as it does when it's a simple PLL and not a CDR
<sb0>
in fact the transceivers have a CDR lock output, but it's so buggy that they tell you not to use it
<cr1901_modern>
sb0: Do chips external to the FPGA exist for CDR (superior to the primitives) that provide a nice interface to the FPGA?
<sb0>
for ethernet there is tbi
<cr1901_modern>
besides* Ethernet
<sb0>
I wonder if you could roll your own CDR with a delay line (similar to my tdc core), DAC and VCXO...
<cr1901_modern>
vcxo?
<sb0>
voltage controlled crystal oscillator
<cr1901_modern>
Ahh, it's like a VCO except better. And with a crystal.
<sb0>
it's a crystal oscillator that can be slightly tuned
<cr1901_modern>
And I have that tdc paper of yours somewhere. Should prob finish reading it
<cr1901_modern>
Guess it doesn't matter if you use a high-bit DAC, but I don't care for the idea of discretizing the VCO input. It adds another
<cr1901_modern>
layer of jitter _on top of_ the jitter that will inevitably exist anyway
<sb0>
yes. so things are never perfect. the question is - does the complete system work or not?
<sb0>
and you can maybe filter that "jitter" with a simple rc filter.
<cr1901_modern>
does the complete system work or not? <-- worth a try if you're totally fed up w/ Xilinx' "incompetence"
<cr1901_modern>
you can maybe filter that "jitter" with a simple rc filter. <-- Never tried it. I just remeber "6 db SNR per bit", assuming a perfect DAC (which of course doesn't exist)
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<rjo>
sb0: the range bein narrow and locking to multiples are not mutually exclusive for a cdr afaict.
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<larsc>
ffiw, altera has all those things. cdr lock indicator, constraints propagation
<larsc>
fwiw
<larsc>
and it is quite useful to have the lock indicator since you can keep the parallel logic in reset until the cdr has locked
<larsc>
on Xilinx I've had issues with the FIFO levels for different lanes diverging since the CDRs where running at different rates while trying to lock
<larsc>
so you basically have to wait until you receive a good comma signal on all lanes, then reset the FIFOs and then ignore the garbage that you receive while the reset is asserted
<rjo>
ack. but i can see no way for CDR to detect locking to the wrong rate. a 2G RX will lock to a 1G stream. you can only detect that at the coding level.
<rjo>
with FIFO you mean the elastic buffers?
<larsc>
yes. It's a FIFO if you don't use the character insertion/removal feature
<rjo>
as i see it, an EB (depending on the implementation) either has a different reset condition from a plain FIFO and no flow control at all or has different flow control from a plain FIFO.
<rjo>
the character insertion/removal being the "no flow control"
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<bb-m-labs>
build #1786 of artiq is complete: Failure [failed conda_install conda_remove] Build details are at http://buildbot.m-labs.hk/builders/artiq/builds/1786 blamelist: whitequark <whitequark@whitequark.org>
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<GitHub39>
[buildbot-config] whitequark force-pushed master from c4a6a2d to 993cc73: https://git.io/v1foL
<GitHub39>
buildbot-config/master b403183 whitequark: Temporarily disable most steps for the artiq builder.
<bb-m-labs>
build #1787 of artiq is complete: Exception [exception conda_install_local] Build details are at http://buildbot.m-labs.hk/builders/artiq/builds/1787 blamelist: whitequark <whitequark@whitequark.org>
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<GitHub12>
[buildbot-config] whitequark force-pushed master from 993cc73 to 1b53fe0: https://git.io/v1foL
<GitHub12>
buildbot-config/master 902f7f2 whitequark: Temporarily disable most steps for the artiq builder.
<bb-m-labs>
build #1789 of artiq is complete: Exception [exception interrupted board_unlock conda_remove] Build details are at http://buildbot.m-labs.hk/builders/artiq/builds/1789 blamelist: Sebastien Bourdeauducq <sb@m-labs.hk>
<bb-m-labs>
build #1790 of artiq is complete: Exception [exception conda_build board_unlock conda_remove] Build details are at http://buildbot.m-labs.hk/builders/artiq/builds/1790 blamelist: Sebastien Bourdeauducq <sb@m-labs.hk>
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<bb-m-labs>
build #1791 of artiq is complete: Exception [exception board_lock board_unlock] Build details are at http://buildbot.m-labs.hk/builders/artiq/builds/1791 blamelist: Sebastien Bourdeauducq <sb@m-labs.hk>
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<GitHub-m-labs>
[buildbot-config] whitequark force-pushed master from f3d4d73 to e0c39ff: https://git.io/v1foL