<davidc__>
sb0: that and "oh, that bank of buttns you get to by pressing shift-3"
<davidc__>
sb0: I mean, its obvious. Shift-1 goes back to the main screen, shift-2 crashes the application unless you are using this specific hardware that nobody has, so don't do that one, then shift-3 gets to the screen you want
<davidc__>
(actual behaviour of a radio system I used in the past)
<sb0>
cr1901_modern, link where?
<cr1901_modern>
sb0: On the misoc repo, under the "how to install gcc" section
<sb0>
FelixVi, the artix7 transceivers are 6.6gbps max. and 10G ethernet is relatively uncommon and expensive.
<FelixVi>
sb0: it's a 4-lane xaui intf
<FelixVi>
something like 3 gbps each lane
<sb0>
depends which
<FelixVi>
GMII
<sb0>
with 10g sfp it's not that
<FelixVi>
so you're right if you go directly to sfp things are different
<FelixVi>
yeah, I keep forgetting that
<FelixVi>
sb0: did you write the dfi bus by any chance?
<sb0>
yes
<FelixVi>
the address logic is what gives me a headache right now
<FelixVi>
in pipistrello it's super fast, but on the saturn platform that becomes the bottleneck
<FelixVi>
I don't understand why
<FelixVi>
same optimization setting... I am playing with those now to see if I can get it to go away
<sb0>
incorrect timing constraints?
<FelixVi>
there's just period constraints
<FelixVi>
1 input clock and 5 derived ones
<FelixVi>
so that's unlikely - and the ucf doesn't have anything else
<sb0>
do you have async domains that ise thinks are related when they are not?
<FelixVi>
that might be the case - i am running without resource sharing, without equiv reg removal and with reg balancing now
<davidc__>
FelixVi: there are 10GBASE gearboxes that go from 2x5GBPS (or lower) to 10GBASE modulation suitable for driving a SFP+, but they aren't cheap/easy parts
<davidc__>
probably cheaper to move to an FPGA that has the native transceiver
<FelixVi>
aha, so now it runs at 62.5 MHz rather than just 25 MHz
<FelixVi>
davidc__: there's some xilinx eval boards, but those were also ~2.5k ea (iirc)
<FelixVi>
sb0: but even with that, optimization of the address logic domain is still screwy - per required 8.000 ns -> actual per 8.000 ns
<sb0>
X&A FPGAs with fast transceivers are expensive
<sb0>
rjo, shouldn't there be another sync mechanism on a single board, i.e. standard JESD204 sync?
<GitHub195>
[smoltcp] phil-opp commented on issue #75: @whitequark I think the most important options are implemented now (message type, requested ip, server identifier). Are there any other options that we need? Other things that I should add/change? https://github.com/m-labs/smoltcp/pull/75#issuecomment-346603933
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<sb0>
rjo, FYI: I put the RTMs on Sayma 1 and 2, and they're now clocked at 100MHz with the SynthNV
<sb0>
the signal level and parameters other than the frequency are the same as they were with the FMC DAC cards
<rjo>
sb0: i don't get what you have in mind. the "other" sync mechanism consists of (a) aligning SYSREF to RTIO plus (b) implementing subclass 1 in jesd204b
<sb0>
the "other" is (b)
<sb0>
that would sync the two DACs on a board, right?
<rjo>
that would only give you alignment between the two dacs on a rtm.
<sb0>
yes
<sb0>
but that's the first step
<rjo>
(a) and (b) are independent
<sb0>
yes
<sb0>
my understanding is that _florent_ should do (b). but only one DAC works on his board.
<rjo>
afaik (b) is with _florent_ and (a) is with us. (b) can be verified with a single DAC using (a) and RTIO
<rjo>
what's the triage/diagnosis of the other DAC?
<_florent_>
rjo: the SERDESPLL is not locking
<sb0>
whitequark, have you tried artiq-2 and the switch?
<rjo>
_florent_: and that is after applying the changes that greg implements on the power supplies and the clock termination?
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<felix_>
rjo: hmm, any reason that the xilinx-xc7.cfg tcl file in openocd is in the cpld folder and not in the fpga folder?
<rjo>
felix_: when i started this, there was only the virtex2 stuff in the cpld folder already. and there was no fpga folder. i followed that lead. someone else then did a fpga folder. if you transition all the configs and sources that's fine by me.
<felix_>
ok
<rjo>
but imho those categories are a bit weird anyway. i'd do it either by manufacturer or merge cpld/fpga.