<sb0>
rjo, which dds chip do we have on the urukul for opticlock? I suppose we don't write a driver for the other one?
<sb0>
whitequark, how would you make the buildbot use the board lock files?
<rjo>
sb0: i'd like to accelerate the progress on that arp issue. it's just being pushed around. and having to wait for shipping now again before any other action is taken does not help. just spend the dozen quid and try to reproduce it.
<sb0>
that's not the arp issue
<rjo>
yes. the switch issue.
<rjo>
or more general: smoltcp issues.
<rjo>
keep in mind that this keeps ARTIQ borderline unusable for many.
<rjo>
sb0: see the wiki for what opticlock uses.
<sb0>
the wiki doesn't give a clear decision for the opticlock dds chip
<rjo>
it's the AD9912. could you update the wiki then?
<sb0>
done. who will write the driver for the other chips and the various other non-opticlock features of the board?
<rjo>
there is only one other chip. and which features do you mean?
<sb0>
there are many and it has become very complex. is everything on that board for opticlock or nu-servo?
<cr1901_modern>
I see... misoc normally protects you from having to use CSRBankArray. I am pretty sure that submodules are recursively scanned for "get_csrs()" though
<cr1901_modern>
not just immediate children
<sb0>
_florent_, how is sayma coming along? do you get an ethernet carrier?
<sb0>
Greg wants me to reset the PHY chip after applying the TX clock, but the reset is only accessible from the MMC as far as I can tell ...
<shuffle2>
removing the middle module would fix it. adding a different immediate child with csrs would allow codegen to succeed and silently drop the grandchild csrs
<cr1901_modern>
CSRWrapper doesn't have a get_csrs() method. Add one by subclassing w/ AutoCSR
<cr1901_modern>
and try that
<cr1901_modern>
i.e. class CSRWrapper(Module, AutoCSR):
<shuffle2>
cr1901_modern: yea i had tried that actually, doesn't change anything
* cr1901_modern
sighs heavily
<cr1901_modern>
why can't something be easy
<cr1901_modern>
I don't have time right now to look deep into it, sorry
<shuffle2>
np
<cr1901_modern>
"lambda name, mem: 0" <-- I don't like this. You don't provide a memory range to which your csr devices should respond to
<shuffle2>
well, they respond to offset 0 starting from axi space on the zynq. i've made some test design with 3 csrs and it seems to work fine
<cr1901_modern>
I would've expected something like csr_map = { "csr_test" : 0 }
<cr1901_modern>
But I guess "0" would work
<cr1901_modern>
in any case, not sure why it's not finding your children, I am 90% positive get_csrs() recurses into children (if get_csrs() exists as a method, which it doesn't in CSRWrapper)
<shuffle2>
the problem is that the submodule must be named at the intermediate level
<shuffle2>
using self.submodules += ThingWithCSRs() results in scan finding that it has get_csrs, but it doesn't actually add them for some reason...
<shuffle2>
it seems explicitly not supported: _make_gatherer will not descend _submodules, which is the only way it could get to the needed depth
<shuffle2>
well not the only way, but the most intuitive :)
<_florent_>
sb0: i'm on it, sorry no new for now, i try to get serwb working in all situations, then clocking, then i can give a try to ethernet
<_florent_>
news
<_florent_>
sb0: for ethernet, IIRC Greg tested it successfully, do you know where we can find the code he tested?
<sb0>
_florent_, just emailed it to you
<_florent_>
sb0: ok thanks, have you tested it yourself?
<sb0>
I just have this messy VHDL file. for anything else please email Greg directly
<sb0>
no
<_florent_>
ok
<sb0>
ah and a few other vhdl sources. second email coming.
<_florent_>
sb0: i just asked greg for the full project
<_florent_>
sb0: but you can stil send me the others files
<sb0>
sent you all I have (3 vhdl files)
<_florent_>
sb0: I'd like to speed P&R for the sayma work i'm doing (sayma_amc takes up to 15min), i'd like to remov the second cpu since unused, analyzer, rtio, do you know where i can do that easily?
<_florent_>
sb0: haven't yet tried, just asking
<sb0>
_florent_, you can build the bare misoc targe
<sb0>
t
<sb0>
but I think the runtime won't compile without rtio
<sb0>
or the second cpu
<sb0>
you could spin another firmware though, that uses libboard and runs the clocking code
<_florent_>
ok thanks, i'll try to see what i can easily do
<whitequark>
_florent_: it should be fairly easy to cfg() off rtio and second CPU
<whitequark>
if you want I'll guide you on doing it
<_florent_>
whitequark: thanks, then i'm going to remove them from gateware and report you the compile errors i have
<sb0>
_florent_, well that doesn't work here. did you patch the code?
<sb0>
_florent_, by the way if you want to try on the boards we have here (3 of them, and sayma 1 and 3 have rtms) your ssh account still works
<sb0>
sayma 1 and 2 usually die after ~hours from the 1V8 bug and to fix this all boards can be power cycled with echo > /dev/ttyACM0
<_florent_>
sb0: ah, yes i probably changed something in the firmware (i'm working in my branch), let me apply that. (but i think there are still initialization issue from time to time that i have to look at)
<sb0>
whitequark, you don't need vivado for the csv
<sb0>
use --no-compile-gateware when building artiq and it skips the vivado part
<sb0>
you can also use vivado on the lab computer if needed
<sb0>
I somehow managed to crash the ftdi chip, too
<sb0>
sigh
<sb0>
bugs, bugs, bugs, bugs and more bugs
rohitksingh_work has quit [Read error: Connection reset by peer]
<whitequark>
a vivarium
<whitequark>
sb0: HAS_DRTIO is conditional on HAS_RTIO, right?
<_florent_>
sb0: ok,for ddr3 failing, it's something similar to what i have (0:512-520 is already wrong since max is 512, need to see if it's an issue in the software or the gateware)
<_florent_>
sb0: ok for the serwb test, i continue work on my side and do more testing
<_florent_>
whitequark: have you been able to look at disabling rtio/cpu in runtime?
<whitequark>
_florent_: finishing it
<whitequark>
will be ready in a moment
<_florent_>
whitequark: ok great
<_florent_>
whitequark; i'm maybe asking too much... :) but is is easy to also disable ethernet in the runtime??... (this would allow me to build from BaseSoC and not MiniSoC)
<_florent_>
is it
<_florent_>
whitequark: if that's not trivial, don't bother with that, not sure it takes a lot more time to build MiniSoC vs BaseSoC. But it would maybe reduce runtime size a bit since no ethernet/smoltcp support.
<whitequark>
_florent_: it's quite trivial
<whitequark>
but let me do it piece by piece
<_florent_>
whitequark: yes of course
mumptai has quit [Remote host closed the connection]
rohitksingh has joined #m-labs
rohitksingh has quit [Quit: Leaving.]
<_florent_>
sb0: strange you were not able to get serwb working, here i've not been able to get it failed for today while doing my tests (20/30 inits), we'll figure that out when clocking will be working
<rjo>
_florent_: what's your vivado version?
<_florent_>
rjo: 2017.2
<_florent_>
rjo: and yours?
<rjo>
_florent_: same
<_florent_>
rjo: ok, possible we don't have the exact same sources, I'll see that later
<rjo>
_florent_: could you have a quick look at my response from yesterday re the eth phy layout dw?
<_florent_>
rjo: sure, i thought i had answered
<_florent_>
rjo: hmm not able to find it, was it a mail or github issue?
<rjo>
"between the phy and the mac? i.e. eth_phy_layout()?"
<rjo>
"that has 8 all over the place."
<_florent_>
yes but i'm trying to find your mail/issue, you have a link if it's an issue or email subject?
<_florent_>
rjo: on sayma_rtm, we have spis with different cs polarities (hmc830 active high, hmc7043 active low), would you be ok that i add support for different cs_polarity in SPIMaster
<_florent_>
rjo: or maybe better doing that outside for now...
rohitksingh has joined #m-labs
<rjo>
_florent_: no mail or issue. i am writing the 1000Base-X PHY (PMA/PCS).
<_florent_>
rjo: ah ok it was on irc...
<_florent_>
rjo: so I'm using dw=32 when using the wishbone interface
<rjo>
_florent_: sure. but keep in mind that the SPIEngine (below the CSR SPI Master) is also used in ARTIQ as an RTIO SPI Master and accesses that stuff differently. but afaict it should be fine and compatible to have cs_polarity undriven in that case.
<_florent_>
but dw=8 with the hardware udp/ip stakc
<_florent_>
stack
<_florent_>
do you need to know more about dw?
<rjo>
_florent_: but the MAC (which we use in MiSoC and ARTIQ) does dw=8 (e.g. gmii etc) everywhere, no?
<_florent_>
ah ok, and you want to simplify code?
<rjo>
_florent_: i want to know whether this will work and has been tested with dw=16
<rjo>
i.e. if the MAC can handle a PHY with dw=16
<_florent_>
ok i see, let me look at the code
<rjo>
... or whether i have to gearbox it. e.g. mac.last_be looks problematic.
<_florent_>
rjo: code seems to be generic, except for delimiters
<_florent_>
(delimiters = last_be)
<_florent_>
but i don't think i tested with dw > 8
<_florent_>
for the phy
<_florent_>
with the 1000 Base-X PHY you have 16bits @ 62.5 MHz?
<_florent_>
it's not possible to run the mac at 8bits @ 125Mhz and keep 16bits in the phy?
<_florent_>
if you want to have a phy with dw=16, i think the only thing you'll have to modify is last_be and use 2 bits instead of one
<rjo>
ok. so it's either gearbox or change/upgrade last_be handling.
<_florent_>
yes
FabM has quit [Quit: ChatZilla 0.9.93 [Firefox 52.3.0/20170811091919]]
_rht has quit [Quit: Connection closed for inactivity]
rohitksingh has quit [Ping timeout: 255 seconds]
<_florent_>
sb0: just for info, serwb seems reliable here, haven't been able to get a failure while testing others things today
<_florent_>
sb0: i got hmc830 spi working (with a small modification misoc's spi), i'm now testing hmc7043
<_florent_>
misoc's spi / to misoc's spi
mumptai has joined #m-labs
<GitHub93>
[smoltcp] edef1c commented on issue #3: Yeah, I need to find some spare time and probably go over some more details with you, but I've got a packet parser and stuff going, I don't think there's all *that* much work involved in integrating this — I'm mostly worried about testing it sufficiently exhaustively https://git.io/vFczA
<GitHub196>
[smoltcp] dlrobertson commented on issue #3: @edef1c Do you have a fork and branch you're working on?... https://git.io/vFcol
<GitHub137>
[smoltcp] dlrobertson commented on issue #3: @edef1c Do you have a fork and branch you're working on?... https://git.io/vFcol
<whitequark>
_florent_: were you able to build everything without rtio kernelcpu and ethmac?
<_florent_>
whitequark: haven't tested yet...
<_florent_>
whitequark: i was expecting to need to rebuild amc for serwb but since it's working... but that will be useful for later
<whitequark>
ah ok
<shuffle2>
is there a (builtin) way to treat a group of platform pins as a Record? (i'd like to have the pins be the "master" side instead of the slave)
<_florent_>
whitequark: that's working fine and a lot faster! : runtime ~10x smaller (so 10x faster to load...) and gateware 4x smaller (less than 5 minutes build) by removing ethernet, kernel cpu and rtio
<_florent_>
whitequark: great for the things i'm working on
<shuffle2>
cr1901_modern: yea, but i'd like to put the direction info into the Subsignal
<shuffle2>
inverting the directions in my Record does what i want, it's just counter intuitive
<whitequark>
_florent_: superb
<whitequark>
_florent_: oh you can also make ksupport.bin empty
<whitequark>
just hack the build system locally to do that
<whitequark>
there's no good way to do it in the build system anyway
<whitequark>
that should shave runtnime size maybe 2x more
<_florent_>
whitequark: that's already fine, runtime is now 40KB and load in a few seconds (was > 400KB before)
<whitequark>
oh right that's because I replaced most of it with while(true)
<whitequark>
and it's built with LTO
<_florent_>
whitequark: thanks for you time on that
<whitequark>
yw
<GitHub30>
[smoltcp] whitequark pushed 1 new commit to master: https://git.io/vFcHJ
<GitHub30>
smoltcp/master 198fe23 Philipp Oppermann: Redesign the phy::Device trait to avoid Drop impls.