sb0 changed the topic of #m-labs to: ARTIQ, Migen, MiSoC, Mixxeo & other M-Labs projects :: fka #milkymist :: Logs http://irclog.whitequark.org/m-labs
<whitequark> sb0: okay, I can look for that.
<GitHub148> [smoltcp] whitequark commented on issue #69: @dlrobertson The updated API doesn't look quite right. Shouldn't you be binding to the identifier field in the IP header rather than IP endpoint? Imagine you are implementing a traceroute program. With the current API this is completely impossible. https://git.io/vFCA4
<GitHub115> [smoltcp] dlrobertson commented on issue #69: > To send and receive ICMP messages that are not associated with a specific TCP/UDP port number (e.g., Echo, Echo Reply, Timestamp, Timestamp Reply, Information Request, Information Reply), the socket has to be bound to a specific ICMP identifier. The ICMP identifier is a 16-bit field present in bytes 5/6 in the header of these messages. Only messages containing the right identifier can be sent or rec
<GitHub49> [smoltcp] whitequark commented on issue #69: Ah, I see. Yes, I think a dedicated enum `IcmpEndpoint` would be best. https://git.io/vFCxe
<GitHub151> [smoltcp] dlrobertson commented on issue #69: How important is it to keep the standard `bind` API? E.g. How bad would it be if we ended up with something like.... https://git.io/vFCx9
<GitHub160> [smoltcp] whitequark commented on issue #69: There's no "standard bind API", we do not try to implement POSIX. There aren't ICMP sockets in POSIX anyway. So, do the most clear thing. https://git.io/vFCxd
<GitHub189> [smoltcp] whitequark commented on issue #69: There's no "standard bind API", we do not try to implement POSIX or abstract over different types of sockets. There aren't ICMP sockets in POSIX anyway. So, do the most clear thing. https://git.io/vFCxd
<GitHub134> [artiq] whitequark pushed 1 new commit to master: https://github.com/m-labs/artiq/commit/fcd660d682d0c55e97c2e3483401f0a433793b28
<GitHub134> artiq/master fcd660d whitequark: runtime: remove accidentally deleted code.
<bb-m-labs> build #885 of artiq-board is complete: Success [build successful] Build details are at http://buildbot.m-labs.hk/builders/artiq-board/builds/885
<bb-m-labs> build #608 of artiq-win64-test is complete: Warnings [warnings python_unittest] Build details are at http://buildbot.m-labs.hk/builders/artiq-win64-test/builds/608 blamelist: whitequark <whitequark@whitequark.org>
<bb-m-labs> build #1771 of artiq is complete: Success [build successful] Build details are at http://buildbot.m-labs.hk/builders/artiq/builds/1771
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<GitHub12> [smoltcp] pothos opened issue #70: Server example does not work anymore https://git.io/vFWTw
<GitHub11> [smoltcp] pothos commented on issue #65: Maybe this is now a bit more readable? I have included the wrapping cases in the test. In wire.rs I had to make the two wrapping subtractions explicit because otherwise sending gave panics in debug mode. https://git.io/vFWLc
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<sb0> _florent_, sayma1 is back online on our server so you can try serwb yourself
<sb0> it still won't initialize ...
<sb0> it seems that the way to crash the ftdi chip is to attempt to use openocd with the fpga unpowered. then it's broken until the USB cable is unplugged and plugged again.
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<shuffle2> suggestion: maybe throw an error when migen encounters an object within sync/comb/etc list which it doesn't understand?
<shuffle2> just debugged back to some disappearing logic caused by map() in the list...when it should have been list(map())...
<shuffle2> (or call the generators...or both)
<_florent_> sb0: I'll finish getting hmc7043 and ad9154 support tomorrow on my board. Once done, try to understand the ddr3 issue. And then we can try to understand why serwb seems to fail on your boards
<sb0> shuffle2, actually missing logic? not some error?
<sb0> do you have a repro?
<sb0> whitequark, any progress on the networking bugs?
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<GitHub33> [sinara] marmeladapk pushed 1 new commit to master: https://github.com/m-labs/sinara/commit/9eaa540193d840bebd9f604b551b8f1512e78662
<GitHub33> sinara/master 9eaa540 Paweł: Kasli...
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<whitequark> sb0: yes, I've reworked the ARP LRU cache, which is the precondition for fixing the bug