sb0 changed the topic of #m-labs to: ARTIQ, Migen, MiSoC, Mixxeo & other M-Labs projects :: fka #milkymist :: Logs http://irclog.whitequark.org/m-labs
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<GitHub19> [sinara] gkasprow pushed 1 new commit to master: https://github.com/m-labs/sinara/commit/064f973cea4f37f1c71dc95f52fc13059415fe86
<GitHub19> sinara/master 064f973 Greg Kasprowicz: Delete 3U_ADC.PDF
<GitHub16> [sinara] gkasprow pushed 1 new commit to master: https://github.com/m-labs/sinara/commit/75bce24f79b84f645e81d79317561d7eac279a84
<GitHub16> sinara/master 75bce24 Greg Kasprowicz: Add files via upload...
<GitHub197> [sinara] gkasprow pushed 4 new commits to master: https://github.com/m-labs/sinara/compare/75bce24f79b8...a909eb5ce7dc
<GitHub197> sinara/master af7546e Greg: production version of panels for Kasli Urukul and clocker
<GitHub197> sinara/master 92ca635 Greg: schematics ready for design review
<GitHub197> sinara/master 019d396 Greg: Merge branch 'master' of https://github.com/m-labs/sinara
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<sb0> whitequark, any progress on ARP?
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* sb0 just got his amateur radio license
<whitequark> nice
<GitHub30> [smoltcp] whitequark commented on issue #55: Okay, I understand your proposal more clearly now. I will reconsider it. https://github.com/m-labs/smoltcp/issues/55#issuecomment-344815242
<GitHub56> [misoc] sbourdeauducq pushed 1 new commit to master: https://git.io/vF1xi
<GitHub56> misoc/master 9b106de Sebastien Bourdeauducq: liteeth/1000basex: PCS fixes, add link_up output, add configurable more_ack time
<bb-m-labs> build #280 of misoc is complete: Failure [failed conda_build] Build details are at http://buildbot.m-labs.hk/builders/misoc/builds/280 blamelist: Sebastien Bourdeauducq <sb@m-labs.hk>
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<_florent_> sb0: i'm on it
<GitHub175> [smoltcp] raintean opened issue #82: Add support for tun interface? https://github.com/m-labs/smoltcp/issues/82
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<sn00n> hi
<rjo> sn00n: hi
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<sn00n> lurkin around is okay i hope?
<sb0> sure
<sn00n> i'm learning a few basics about ion traps, that's why i'm here - and it's openfpga related :)
<sb0> openfpga?
<sb0> what's the connection between ion traps and openfpga?
<sn00n> like ion traps -> m-labs -> MiGen, MiSoC etc?
<sn00n> like ion traps -> NIST -> ARTIQ -> m-labs -> MiGen, MiSoC etc?
<sn00n> sry
<sn00n> i read about MiGen in ##openfpga
<cr1901_modern> sb0: Bunch of ppl who idle in here also idle in ##openfpga
<cr1901_modern> and vice-versa
<GitHub158> [sinara] gkasprow pushed 1 new commit to master: https://github.com/m-labs/sinara/commit/10a89411568727a46b955e81e61d0ece5ed6e87c
<GitHub158> sinara/master 10a8941 Greg: shematic update
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<FelixVi2> mithro, are you around?
<mithro> FelixVi2: kinda
<FelixVi2> mithro, can you let me know when you have a second? I'm still struggling with lm32 toolchains and am looking at hdmi2usb-litex now
<FelixVi2> Maybe this is a more general question anyways - I've had luck getting the original Lattice toolchain going, build a lm32 implementation, modified the verilog for Spartan-6, compiled code and got it running --- BUT I'm sol as far as getting misoc to go under Windows (CygWin64)
<mithro> Don't use windows
<FelixVi2> mithro, It's a longer story, but I will be using windows -.- Even if it makes life painful
<cr1901_modern> I don't use cygwin, so I can't help
<mithro> FelixVi2: I can't help if you are using windows, I have no idea with that
<cr1901_modern> Just to preemptively get that out of the way :P
<FelixVi2> mithro, maybe that's not entirely true - I could use linux as long as I can cross compile so that others can compile lm32 code under windows
<FelixVi2> but I haven't worked that out yet
<mithro> FelixVi2: Get stuff working on Linux first and then we can figure out the Window stuff later?
<FelixVi2> mithro, that may be the best way to go. I don't know enough about misoc to attempt getting it to go with python 3.6
<mithro> FelixVi2: On Linux, just follow the instructions I linked and you should have a working litex environment in under an hour
<mithro> FelixVi2: complete with toolchains, Python, OpenOCD, etc
<FelixVi2> mithro, cool, thanks a lot!
<mithro> FelixVi2: Just make sure you do a "export CPU=lm32" rather than an "export CPU=or1k" if you want the lm32 CPU core
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<cr1901_modern> rjo: Platform tests have been fixed. Other tests use setattr, btw (most likely because they predate subTest). Once you sign off on this one I'll add the toolchain tests and fixup the
<cr1901_modern> setattr tests as subtests if you wish
<GitHub192> [migen] jordens pushed 4 new commits to master: https://git.io/vFDMN
<GitHub192> migen/master 210c4fd William D. Jones: test/platform: test_roach is an expected failure due to lack of default clock.
<GitHub192> migen/master 71915c5 William D. Jones: test: Add Platform-specific tests.
<GitHub192> migen/master 36e82d3 William D. Jones: test/platform: Refactor tests as subTests.
<cr1901_modern> Additionally, I added my third and final PR I originally meant to send
<rjo> cr1901_modern: thanks. opinionated (i.e. with carefully chosen arguments) cleanup work is highly welcome.
<bb-m-labs> build #202 of migen is complete: Success [build successful] Build details are at http://buildbot.m-labs.hk/builders/migen/builds/202
<cr1901_modern> with carefully chosen arguments? For these rounds of PRs (I admit it's been a while since I contributed :P), I've been sending them, expecting feedback/changes, tweak, make suggestions if something seems off, repeat.
<rjo> cr1901_modern: what i mean is: if you notice something in the code and are confident that you could improve it, then please go ahead.
<cr1901_modern> rjo: We agree that the way the icestorm backend is right now (using lists for yosys script/command output) is what you want for the remaining backends?
<rjo> yes
<cr1901_modern> Okay cool. Btw, https://github.com/m-labs/migen/pull/87 When you get the chance
<GitHub150> [artiq] philipkent opened issue #850: Log messages not printed in scheduled experiment https://github.com/m-labs/artiq/issues/850
<FelixVi2> is misoc always based on llvm or can it use gcc compilers as well?
<GitHub157> [smoltcp] whitequark commented on issue #82: What's the point? https://github.com/m-labs/smoltcp/issues/82#issuecomment-345078808
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<FelixVi2> when trying to compile the papilio_pro target, i get this:
<FelixVi2> lm32-elf-ld: bios.elf section `.rodata' will not fit in region `rom'
<FelixVi2> should this be working or did the basesoc get larger and it doesn't fit on a papilio any more?