sb0 changed the topic of #m-labs to: ARTIQ, Migen, MiSoC, Mixxeo & other M-Labs projects :: fka #milkymist :: Logs http://irclog.whitequark.org/m-labs
<GitHub61>
[smoltcp] whitequark commented on issue #82: Yes. Tap interfaces are software emulation of layer 2 interfaces (Ethernet in our case) so we can handle them with EthernetInterface. However, tun interfaces are software emulation of layer 3 interfaces (TCP/UDP/IP directly), so we would need an alternative to EthernetInterface that works on layer 3. We can implement that, but why should we? https://github.com/m-labs/smoltcp/issues/82#issuecomment-34
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<FelixVi>
_florent_: are you around?
<cr1901_modern>
FelixVi: Patience. IRC is async.
<FelixVi>
cr1901_modern: yeah, I can work on another platform implementation in the meantime ;)
<FelixVi>
cr1901_modern: have you heard about the path resolution issue? I can help out with that and/or do some more testing as well
<cr1901_modern>
which path resolution issue? I've lost count
<FelixVi>
there might be a couple more things inside generated batch files that we haven't touched yet
<cr1901_modern>
I just want cygwin to work so I can forget about it again lol
<FelixVi>
the posix vs win path thing
<cr1901_modern>
Batch files should be fine; user is expected to run the batch file from within the build directory
<cr1901_modern>
it'll fail otherwise
<FelixVi>
yeah, everything is working fine. I get one error that a file is not found, but that's just the ISE settings.bat that is called from with the build batch file
<cr1901_modern>
A. which file?
<cr1901_modern>
B. There is absolutely nothing we can do about that anyway
<FelixVi>
are there any examples how a kernel file is generated for misoc?
<FelixVi>
saturn platform is still broken (I'll try another FPGA board tomorrow), so I'm using a Papilio for now
<FelixVi>
is there a way that migen can run the compiler for kernels or are you supposed to generate Makefiles yourself?
<FelixVi>
*migen or misoc
<FelixVi>
all I'm trying to get going for now is a single puts("Hello World"), I assume that's a good start
<FelixVi>
or maybe the blinkie example shown at orconf2014
<FelixVi>
if anybody has a suggestion, I'll check IRC logs in the morning
<FelixVi>
good night
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<_florent_>
FelixVI: has you tested the generated bitstream at 81.333 even with the timing errors?
<_florent_>
has/have
<_florent_>
FelixVI: if you change the cpu freq, you will have to adjust others parameters yes.
<_florent_>
FelixVI: you can try to change rd_bitslip, wr_bitslip, dqs_ddr_alignment if frequency is changed
<_florent_>
FeflixVI: for debug, you can reduce l2 size to minimum (try to reduce until misoc complains), add some printf to memtest to see what is read, what was expected on error check, then you can post results here or try to understand what is going on.
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<key2>
hi
<cr1901_modern>
Idle thought: What happened to key1?
<key2>
who that
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<_florent_>
cr1901_modern: the caterpillar has turned into a butterfly :)
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<cr1901_modern>
_florent_: Good point
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<FelixVi>
_florent_: yes, I tried the image at 81.333 MHz - didn't work
<FelixVi>
timing must be different between the two speedgrades
<FelixVi>
can you help me tweak the memory controller?
<FelixVi>
I just need to setup a bunch of stuff as this is another computer
<FelixVi>
_florent_: is this problem a thing because the sdram controller i/o aren't registered?
<FelixVi>
I guess I'm just not sure what I am trying to tweak if the design meets timing
<FelixVi>
or is there something that can't have a timing constraint?
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<FelixVi>
ok, so how are you supposed to compile misoc/software/memtest ?
<cr1901_modern>
grep for "extra software packages"
<FelixVi>
adding it as builder.add_software_package("memtest") yields this error
<cr1901_modern>
oh nevermind can't help you then :)
<_florent_>
FelixVi: the problem is not with synthesis but with controller parameters. Now that you are able to see returned data, you play with rd_bitslip, wr_bitslip and dqs_ddr_alignment and see if it's better
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<FelixVi>
yeah, hopefully that's fixable
<FelixVi>
i still can't compile memtest, though
<FelixVi>
the non-bios version appears to be missing libraries
<FelixVi>
sb0: should memtest as software package be functional? If so, where does it get all its functions from? the linker says it can't find them
<FelixVi>
_florent_: I'm not having much luck with dqs_ddr_alignment or bitslip
<FelixVi>
what I find weird is that no matter what I do, the random address test (last one in bios memtest) is alsways off by 1
<FelixVi>
the other question I have is what if the soc configuration and FPGA mapping changes? Do you have to sit sown every time and fiddle around with memory timing?
<FelixVi>
or does this keep working assuming you hit timing relatively centered
<cr1901_modern>
"Do you have to sit sown every time and fiddle around with memory timing?" Probably not
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<FelixVi>
cr1901_modern: I hope so... Something here doesn't check out
<FelixVi>
It's probably another detail I'm missing
<FelixVi>
but it's like address and data serdes have a weird phase shift
<FelixVi>
pll3 has an actual period of 2.666 ns while pll2 has 7.972 ns
<FelixVi>
I think that's the problem, so it's gonna be hard to align data off the 2x clock and shifted 2x clock