00:36 <mkk_> [Dmitry Belimov, skywater-pdk] Hi

07:16 <mkk_> [Kuan-Wei Hou, skywater-pdk] Hello, everyone. I would like to use the pdk in a undergraduate course to teach students analog circuit. I have git-cloned the pdk from Github and execute "make". However, I do not see any files in the directory "https://github.com/google/skywater-pdk/https://github.com/google/skywater-pdk/tree/master/libraries/sky130_fd_sc_hd/latest". It's empty. Since I am a hardware guy and not familiar with the pyth

10:03 <mkk_> [diadatp, skywater-pdk] If anyone's having trouble getting the pdk setup or wants to get started as quickly as possible, I've packaged rc2 of the openlane flow and the high density subset of the skywater pdk into a single Docker image.

10:04 <mkk_> ```docker run -it -v $(pwd):/openLANE_flow/designs/spm/runs -u $(id -u $USER):$(id -g $USER) diadatp/openlane_pdk:rc2```

10:04 <mkk_> [diadatp, skywater-pdk] Run the command below in a clean new directory and after a 350MB download you will dropped into a shell with the openlane flow.

10:04 <mkk_> After that you could run the following to harden the spm design.

10:04 <mkk_> ```./flow.tcl -design spm```

10:05 <mkk_> [diadatp, skywater-pdk] I've tested this on Ubuntu 18.04 and its mostly used as a reproducible build environment for remote VMs.

10:06 <mkk_> [Iain Craig, skywater-pdk] Excellent!

16:59 <mkk_> [Trevor Clarke, skywater-pdk] what's the best practice for bias voltages on multiple fets in a cell? Should I setup voltage rails for them and connect outside the cell (to either an external voltage, on-chip converter, or Vref as appropriate)?

16:59 <mkk_> [Trevor Clarke, skywater-pdk] if so, is there a generally used layer for voltage rails? (metal1?)

17:00 <mkk_> [Trevor Clarke, skywater-pdk] finally, best way to connect that to the poly or locali for the fets? (magic via1/via2, etc. menu items?)

17:01 <mkk_> [Trevor Clarke, skywater-pdk] or just leave the sub-cell as locali and on the upper cell layer deal with the rails? (same question about vias)