clifford changed the topic of #yosys to: Yosys Open SYnthesis Suite: http://www.clifford.at/yosys/ -- Channel Logs: https://irclog.whitequark.org/yosys
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<dmin7> hi, bit of a weird question: are there any logic analyzers (or other hardware products) out there doing sort of "trigger based output filtering", so that you can define certain trigger events, and then you get a 'clean' output with only those events in it?
<ZipCPU> External or internal to the FPGA?
<dmin7> external
* ZipCPU scratches his head
<ZipCPU> I know digilent's "Digital Discovery" is quite scriptable, but I'm not sure if that necessarily means it does or doesn't do what you are looking to do.
<ZipCPU> I know from an internal logic analyzer standpoint, the wbscope that I use and its wbscopc (compressed) cousin may both be configured to do what you are asking.
<dmin7> looks interesting, thx
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<mjoldfield> dmin7 : Could you capture everything and then filter it ?
<ZipCPU> Wouldn't that require a bigger capture memory?
<mjoldfield> ZipCPU: Yes, indeed, but you can then do the filtering at your leisure :)
<dmin7> and you can potentially sample at higher speeds / better resolution, if you know there is not going to be much "signal traffic" and are focused on the timing
<mjoldfield> I've played with an older version of this https://www.saleae.com which was pleasant for simple stuff.
<tpb> Title: USB Logic Analyzers from Saleae - (at www.saleae.com)
<dmin7> (which is kinda what i'm trying to do with the ice40 atm :)
<dmin7> (also why i want to know if it already exists in that form)
<mjoldfield> I think there are problems where you want to filter at capture time, and other ones where it's better to grab everything. I suppose it comes down to how complicated the filter needs to be.
<tpb> Title: SUMP2 100 MSPS 32bit Logic Analyzer for icoBoard+RaspberryPi Black Mesa Labs (at blackmesalabs.wordpress.com)
<dmin7> mjoldfield: yep, there's also this (based on sump2) .. which has nice triggering options http://dangerousprototypes.com/docs/SUMP_logic_analyzer_Verilog_Demon_core_documentation
<tpb> Title: SUMP logic analyzer Verilog Demon core documentation - DP (at dangerousprototypes.com)
<dmin7> but that's still just triggering, no filtering as far as i can see
<mjoldfield> dmin7: Yes, I think you're right.
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<jonsmith> anyone around?
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<ZipCPU> yes
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