<TD-Linux> here's the sender "card", also an ecp5 https://www.aliexpress.com/item/32852551698.html
<TD-Linux> it's the best use of pcie ever. it only uses it for power. configuration and video input is dvi and usb
<rombik_su> There's a room for improvement - they should try to use it for just mechanical purpose on the next spin
<azonenberg> rombik_su: lol
<gruetzkopf> hm i wonder how much ram the receive card has
<gruetzkopf> imagine: vexriscv, linux, /dev/console on led matrix
<azonenberg> Anybody CONUS based interested in a free 7z020-1clg484 (i think, have to double check)? Only catch is that it's a pull so you'd have to reball
<azonenberg> but it would be removed from working hardware and fully cleaned of old solder and flux
<azonenberg> I'm scrapping some boards from a customer, decapping one because i've never seen a nude zynq before
<azonenberg> but the other one is going in the trash unless someone wants it
emeb_mac has joined ##openfpga
bwidawsk has quit [Read error: Connection reset by peer]
bwidawsk has joined ##openfpga
<q3k> TD-Linux | do you have a suggestion for software/hardware that sends video to it with the stock firmware?
<q3k> nope, not something i wanted/needed
<q3k> i'm interested in knowing how the buffers are arranged
<q3k> if they're more individually switchable than on the S6-based board then this would make for a good boneless glasgow
<rombik_su> q3k: Looks like you'll need additional card like https://www.aliexpress.com/item/32852551698.html and (possible) software from http://colorlight-led.com/colorlight-download.html
<q3k> the ones on the s6 version were mostly hardwired as output which made it meh-tier
<q3k> rombik_su: yes, that much i know
<q3k> rombik_su: but i've never used that hw/sw
<q3k> so i can't vouch if it's actually usable :P
<q3k> iirc marcan worked on reversing the protocol to be able to send data from a normal PC
<q3k> bypassing the windows software and magical sender card
<q3k> anyway, just ordered two of these, they will arrive ~some day
pie_ has joined ##openfpga
pie_[bnc] has joined ##openfpga
<TD-Linux> I expect them to not be switchable but we'll find out
bwidawsk has quit [Ping timeout: 265 seconds]
bwidawsk has joined ##openfpga
pie_ has quit [Quit: pie_]
bwidawsk has quit [Ping timeout: 268 seconds]
bwidawsk has joined ##openfpga
Stary has quit [Ping timeout: 260 seconds]
Stary has joined ##openfpga
pie_ has joined ##openfpga
pie_ has quit [Client Quit]
anticw has quit [Remote host closed the connection]
anticw has joined ##openfpga
X-Scale` has joined ##openfpga
X-Scale has quit [Ping timeout: 265 seconds]
X-Scale` is now known as X-Scale
<marcan> q3k: the ones I got used used some fucked up line protocol that isn't ethernet
<marcan> supposedly *some* firmware versions support direct ethernet sending, but not mine
<marcan> I tried plugging in the sender to my thinkpad and that kernel panicked the box lol
<marcan> I get the feeling they don't packetize like Ethernet, even though they use PHYs
<whitequark> lmao
<whitequark> that... actually seems like um
<whitequark> a remote DoS?
<whitequark> that seems bad.
<marcan> well... if it's not switchable, you need to be plugged in *directly* into the rogue device
<marcan> at which point... they might also just send 12kV your way
<whitequark> that's true
rohitksingh has joined ##openfpga
<azonenberg> q3k: wtf it panicked the box?
<azonenberg> i kinda want to put a sniffer on that and see
<azonenberg> (yay layer 1 packet sniffing)
OmniMancer has joined ##openfpga
bwidawsk has quit [Ping timeout: 255 seconds]
<marcan> azonenberg: I think you mean me, and I was able to get some packets out before the panic
<marcan> it looked like random chunks of RGB data, with weird packet boundaries
<azonenberg> marcan: yeah i mean you
<azonenberg> does it run over 1G or 10G or 100M or what?
<marcan> 1G
<azonenberg> ah ok, i can't (yet) read that off the wire
<marcan> you could just sniff on the PHY pins
<azonenberg> Yeah i know
<azonenberg> I was just thinking, i have an idea for a test fixture using some directional couplers to sniff 1000base-T midspan
<azonenberg> but i'm not sure if i can make it wideband enough to work
<marcan> anyway, I think they just use weird packet framing
<marcan> and the MAC gets very confused
<azonenberg> That sounds very plausible
<marcan> probably bullshit checksums too
<marcan> I think I had to disable a bunch of ethernet features to get any data through
<marcan> that card in the thinkpad wasn't the most well behaved
<TD-Linux> marcan, yeah I would 100% believe it's custom data
<TD-Linux> ethernet packets without IP, or worse
<marcan> it's definitely not "ethernet packets"
<marcan> it's "something" using the Ethernet physical layer
<azonenberg> it's ethernet in the same way that usb3 is pcie
<marcan> "Ethernet packets" would imply sane MAC headers and checksum, which this most definitely does not have
<azonenberg> :p
<marcan> e.g. it would go through a switch
<TD-Linux> ah I see
<marcan> this does not go through a switch :p
<azonenberg> marcan: i kinda wish they would do that
<marcan> yeah
<azonenberg> that would be really nice actually
<TD-Linux> this card is probably differnet, as it claims it survives switches
<marcan> if it survives switches then you can emulate it on a PC for sure
<marcan> also they have a control sideband, so it's not just a flood of RGB data
<TD-Linux> probably not worth doing vs writing my own gateware
<marcan> there have to be *some* headers and stuff
<marcan> there is some open code somewhere for the linsn ethernet protocol
<marcan> the actual one that some cards support
<marcan> but mine definitely don't
<TD-Linux> I suppose I could buy the "pcie" card and RE it. that card is $100 tho
Bike has quit [Quit: Lost terminal]
bwidawsk has joined ##openfpga
<omnitechnomancer> How small could you get a SUBLEQ computer in an FPGA?
<omnitechnomancer> @marc
<omnitechnomancer> marcan:
<omnitechnomancer> clearly you need a layer 1 switch
<azonenberg> omnitechnomancer: when i build latentred, one of my TODO items is a layer-1 packet capture facility
<omnitechnomancer> layer-1 "switches" are a thing apparently :P
<azonenberg> raw ethernet frames with timestamps +/- a couple of ns encapsulated in an outer framing protocol and sent to the host for analysis
<azonenberg> timestamp, actual length, preamble, frame, and fcs
<marcan> omnitechnomancer: yes, they come in a few varieties. DPDT, SPDT, SPST...
<omnitechnomancer> marcan: ethernet ones I mean, I believe for doing test stuff
<sorear> hahaha
<omnitechnomancer> A programmable patch panel can be useful
<omnitechnomancer> I wonder what the smallest viable memory size is for a SUBLEQ machine
<sorear> define "viable"
<sorear> only need a dozen or so states in any interesting model of computation to ask questions beyond current mathematics
<omnitechnomancer> be able to run a practically useful program
<omnitechnomancer> I'd also have to check how one might do memory mapped IO
<omnitechnomancer> might require a trigger address where touching it at all signals that the other address where the actual value is should be used
<omnitechnomancer> since you can't do a straight copy with subleq
<sorear> I mean "practically useful" covers a huge amount of ground
<sorear> you're gonna need a lot of memory to run yosys
emeb_mac has quit [Quit: Leaving.]
lexano has quit [Ping timeout: 240 seconds]
emeb has quit [Quit: Leaving.]
lexano has joined ##openfpga
<omnitechnomancer> The kind of thing you might do on a small microcontroller
Jybz has joined ##openfpga
<TD-Linux> azonenberg, you could sell that and make $$$$ from broadcast people
<TD-Linux> they managed to make a standard that uses RTP/UDP but requires microsecond timing
<azonenberg> lol
Jybz has quit [Quit: Konversation terminated!]
m4ssi has joined ##openfpga
<kc8apf> us timing? That's pretty trivial with 1588 and a good reference
rohitksingh has quit [Ping timeout: 258 seconds]
<gruetzkopf> hm, anyone implement the upcoming 1588 release (CERN white rabbit) yet
Asu has joined ##openfpga
rohitksingh has joined ##openfpga
rohitksingh has quit [Ping timeout: 240 seconds]
<gruetzkopf> http://www.etron.com/manager/uploads/EM63A165TS_v1.4.pdf if that backside-ram on the ecp5 based receive card is the same it has 64MiB of SDRAM
rohitksingh has joined ##openfpga
mickdermack8 has quit [Ping timeout: 258 seconds]
Sprite_tm has quit [Ping timeout: 248 seconds]
mickdermack8 has joined ##openfpga
Sprite_tm has joined ##openfpga
rohitksingh has quit [Ping timeout: 268 seconds]
rohitksingh has joined ##openfpga
_whitelogger has joined ##openfpga
<daveshah> gruetzkopf: I thought it was a EM63_6_165TS which is only 16Mbit unfortunately
fibmod has quit [Ping timeout: 265 seconds]
<gruetzkopf> hm, i'll see once cards hit cpressers shipping location
_whitelogger has joined ##openfpga
rohitksingh has quit [Ping timeout: 260 seconds]
rohitksingh has joined ##openfpga
genii has joined ##openfpga
emeb has joined ##openfpga
Laksen has joined ##openfpga
bwidawsk has quit [Quit: Always remember, and never forget; I'll be back.]
bwidawsk has joined ##openfpga
rombik_su has quit [Read error: Connection reset by peer]
noopwafel has joined ##openfpga
dh73 has joined ##openfpga
Laksen has quit [Quit: Leaving]
OmniMancer has quit [Quit: Leaving.]
fibmod has joined ##openfpga
emeb has quit [Quit: Leaving.]
mumptai has joined ##openfpga
m4ssi has quit [Remote host closed the connection]
<daveshah> Something of note wrt those LED cards - downloading LEDUpgrade_Setup V1.20 from https://www.ledscreenparts.com/product/colorlight-software-download-page/; and extracting it; UpgradePack/RcvUpgrade/ has a load of ECP5 and ECP3 bitstreams in it
andele has joined ##openfpga
andele has left ##openfpga [##openfpga]
rombik_su has joined ##openfpga
<daveshah> Looks from a newer Upgrade (http://www.colorlightinside.com/upload/Support/Software/LEDUpgrade%20SetUp%20V3.0.rar) like the SODIMM form factor i5 and i9 are also ECP5 based, with a 45k in the i9 (but I can't find it for sale anywhere)
<daveshah> Looks like the X1, X3 and X4s senders are also ECP5 45k based.
Asu` has joined ##openfpga
Asu has quit [Ping timeout: 265 seconds]
rohitksingh_ has joined ##openfpga
rohitksingh has quit [Ping timeout: 260 seconds]
rohitksingh_ has quit [Ping timeout: 258 seconds]
rohitksingh has joined ##openfpga
Jybz has joined ##openfpga
rohitksingh_ has joined ##openfpga
rohitksingh__ has joined ##openfpga
rohitksingh has quit [Ping timeout: 260 seconds]
rohitksingh_ has quit [Ping timeout: 265 seconds]
rohitksingh__ has quit [Ping timeout: 265 seconds]
<gruetzkopf> don't do all the reversing before we even have hardware :>
rohitksingh has joined ##openfpga
rohitksingh_ has joined ##openfpga
rohitksingh has quit [Read error: Connection reset by peer]
Asu` has quit [Ping timeout: 240 seconds]
rohitksingh has joined ##openfpga
rohitksingh__ has joined ##openfpga
rohitksingh___ has joined ##openfpga
rohitksingh____ has joined ##openfpga
rohitksingh_ has quit [Ping timeout: 265 seconds]
Asu` has joined ##openfpga
rohitksingh has quit [Ping timeout: 265 seconds]
rohitksingh_ has joined ##openfpga
rohitksingh has joined ##openfpga
rohitksingh__ has quit [Ping timeout: 265 seconds]
dh73 has quit [Ping timeout: 258 seconds]
rohitksingh has quit [Read error: Connection reset by peer]
rohitksingh__ has joined ##openfpga
rohitksingh___ has quit [Ping timeout: 265 seconds]
rohitksingh____ has quit [Ping timeout: 265 seconds]
rohitksingh_ has quit [Ping timeout: 265 seconds]
rohitksingh has joined ##openfpga
rohitksingh has quit [Read error: Connection reset by peer]
rohitksingh has joined ##openfpga
rohitksingh__ has quit [Ping timeout: 265 seconds]
rohitksingh_ has joined ##openfpga
rohitksingh__ has joined ##openfpga
rohitksingh has quit [Ping timeout: 265 seconds]
rohitksingh has joined ##openfpga
rohitksingh has quit [Read error: Connection reset by peer]
rohitksingh_ has quit [Ping timeout: 265 seconds]
rohitksingh has joined ##openfpga
rohitksingh__ has quit [Ping timeout: 265 seconds]
rohitksingh has quit [Read error: Connection reset by peer]
rohitksingh has joined ##openfpga
rohitksingh has quit [Ping timeout: 265 seconds]
rohitksingh has joined ##openfpga
rohitksingh_ has joined ##openfpga
rohitksingh has quit [Ping timeout: 265 seconds]
rohitksingh_ has quit [Ping timeout: 265 seconds]
rohitksingh has joined ##openfpga
rohitksingh_ has joined ##openfpga
rohitksingh has quit [Read error: Connection reset by peer]
rohitksingh has joined ##openfpga
rohitksingh has quit [Read error: Connection reset by peer]
rohitksingh_ has quit [Ping timeout: 265 seconds]
rohitksingh has joined ##openfpga
rohitksingh_ has joined ##openfpga
rohitksingh__ has joined ##openfpga
rohitksingh has quit [Ping timeout: 265 seconds]
rohitksingh_ has quit [Ping timeout: 265 seconds]
rohitksingh__ has quit [Ping timeout: 265 seconds]
rohitksingh has joined ##openfpga
rohitksingh_ has joined ##openfpga
rohitksingh__ has joined ##openfpga
rohitksingh___ has joined ##openfpga
rohitksingh___ has quit [Read error: Connection reset by peer]
rohitksingh has quit [Ping timeout: 265 seconds]
rohitksingh___ has joined ##openfpga
rohitksingh has joined ##openfpga
rohitksingh_ has quit [Ping timeout: 265 seconds]
rohitksingh__ has quit [Ping timeout: 265 seconds]
rohitksingh_ has joined ##openfpga
Bob_Dole has joined ##openfpga
rohitksingh___ has quit [Ping timeout: 265 seconds]
rohitksingh_ has quit [Read error: Connection reset by peer]
rohitksingh_ has joined ##openfpga
rohitksingh has quit [Ping timeout: 265 seconds]
rohitksingh has joined ##openfpga
rohitksingh_ has quit [Ping timeout: 265 seconds]
rohitksingh has quit [Ping timeout: 265 seconds]
rohitksingh has joined ##openfpga
rohitksingh_ has joined ##openfpga
rohitksingh__ has joined ##openfpga
rohitksingh___ has joined ##openfpga
rohitksingh____ has joined ##openfpga
rohitksingh has quit [Ping timeout: 265 seconds]
rohitksingh_ has quit [Ping timeout: 265 seconds]
rohitksingh__ has quit [Ping timeout: 265 seconds]
rohitksingh___ has quit [Ping timeout: 265 seconds]
rohitksingh____ has quit [Ping timeout: 265 seconds]
rohitksingh_ has joined ##openfpga
dh73 has joined ##openfpga
rohitksingh_ has quit [Ping timeout: 265 seconds]
Jybz has quit [Quit: Konversation terminated!]
rohitksingh has joined ##openfpga
rohitksingh_ has joined ##openfpga
rohitksingh__ has joined ##openfpga
rohitksingh___ has joined ##openfpga
rohitksingh___ has quit [Read error: Connection reset by peer]
<rvense> kbeckmann: do you have firmware+bitstream binaries to get pergola to blink or similar?
rohitksingh has quit [Ping timeout: 265 seconds]
rohitksingh_ has quit [Ping timeout: 265 seconds]
<miek> rvense: there's a firmware bin & nmigen code to generate a blinky bitstream @ https://github.com/pergola-fpga/pergola
rohitksingh has joined ##openfpga
<rvense> miek: cool! thanks
rohitksingh__ has quit [Ping timeout: 265 seconds]
rohitksingh_ has joined ##openfpga
rohitksingh__ has joined ##openfpga
rohitksingh___ has joined ##openfpga
rohitksingh has quit [Ping timeout: 265 seconds]
rohitksingh____ has joined ##openfpga
rohitksingh_ has quit [Ping timeout: 265 seconds]
rohitksingh__ has quit [Ping timeout: 258 seconds]
rohitksingh___ has quit [Ping timeout: 265 seconds]
rohitksingh____ has quit [Ping timeout: 258 seconds]
<noopwafel> I had to ln the pergola_fw.bin file to usb_cdc_prebuilt.bin to make it work
rohitksingh has joined ##openfpga
<noopwafel> but otherwise it worked great
rohitksingh_ has joined ##openfpga
rohitksingh__ has joined ##openfpga
rohitksingh___ has joined ##openfpga
rohitksingh has quit [Ping timeout: 258 seconds]
rohitksingh has joined ##openfpga
rohitksingh_ has quit [Ping timeout: 258 seconds]
rohitksingh_ has joined ##openfpga
rohitksingh__ has quit [Ping timeout: 258 seconds]
rohitksingh___ has quit [Ping timeout: 258 seconds]
rohitksingh__ has joined ##openfpga
rohitksingh has quit [Ping timeout: 258 seconds]
rohitksingh___ has joined ##openfpga
rohitksingh has joined ##openfpga
rohitksingh_ has quit [Ping timeout: 258 seconds]
rohitksingh__ has quit [Ping timeout: 258 seconds]
rohitksingh_ has joined ##openfpga
rohitksingh___ has quit [Ping timeout: 258 seconds]
rohitksingh has quit [Ping timeout: 258 seconds]
rohitksingh has joined ##openfpga
rohitksingh__ has joined ##openfpga
rohitksingh___ has joined ##openfpga
rohitksingh____ has joined ##openfpga
rohitksingh_ has quit [Ping timeout: 258 seconds]
rohitksingh has quit [Ping timeout: 258 seconds]
rohitksingh__ has quit [Ping timeout: 258 seconds]
rohitksingh___ has quit [Ping timeout: 258 seconds]
rohitksingh____ has quit [Ping timeout: 258 seconds]
rohitksingh has joined ##openfpga
rohitksingh has quit [Ping timeout: 258 seconds]
rohitksingh has joined ##openfpga
rohitksingh_ has joined ##openfpga
rohitksingh__ has joined ##openfpga
rohitksingh___ has joined ##openfpga
rohitksingh has quit [Ping timeout: 258 seconds]
rohitksingh has joined ##openfpga
rohitksingh_ has quit [Ping timeout: 258 seconds]
rohitksingh_ has joined ##openfpga
rohitksingh__ has quit [Ping timeout: 258 seconds]
rohitksingh___ has quit [Ping timeout: 258 seconds]
rohitksingh has quit [Ping timeout: 258 seconds]
rohitksingh_ has quit [Ping timeout: 258 seconds]
rohitksingh_ has joined ##openfpga
rohitksingh__ has joined ##openfpga
rohitksingh has joined ##openfpga
rohitksingh___ has joined ##openfpga
rohitksingh___ has quit [Read error: Connection reset by peer]
rohitksingh_ has quit [Ping timeout: 258 seconds]
rohitksingh_ has joined ##openfpga
rohitksingh___ has joined ##openfpga
rohitksingh__ has quit [Ping timeout: 258 seconds]
rohitksingh has quit [Ping timeout: 258 seconds]
rohitksingh_ has quit [Ping timeout: 258 seconds]
rohitksingh___ has quit [Ping timeout: 258 seconds]
rohitksingh has joined ##openfpga
rohitksingh_ has joined ##openfpga
rohitksingh__ has joined ##openfpga
rohitksingh___ has joined ##openfpga
rohitksingh has quit [Ping timeout: 258 seconds]
rohitksingh has joined ##openfpga
rohitksingh_ has quit [Ping timeout: 258 seconds]
rohitksingh_ has joined ##openfpga
rohitksingh__ has quit [Ping timeout: 258 seconds]
rohitksingh____ has joined ##openfpga
rohitksingh__ has joined ##openfpga
rohitksingh___ has quit [Ping timeout: 258 seconds]
rohitksingh has quit [Ping timeout: 258 seconds]
rohitksingh_ has quit [Ping timeout: 258 seconds]
rohitksingh____ has quit [Ping timeout: 258 seconds]
rohitksingh__ has quit [Ping timeout: 258 seconds]
rohitksingh has joined ##openfpga
rohitksingh_ has joined ##openfpga
rohitksingh__ has joined ##openfpga
rohitksingh has quit [Ping timeout: 258 seconds]
rohitksingh_ has quit [Ping timeout: 258 seconds]
rohitksingh__ has quit [Ping timeout: 258 seconds]
rohitksingh has joined ##openfpga
rohitksingh_ has joined ##openfpga
rohitksingh__ has joined ##openfpga
rohitksingh has quit [Ping timeout: 258 seconds]
rohitksingh__ has quit [Read error: Connection reset by peer]
rohitksingh has joined ##openfpga
rohitksingh_ has quit [Ping timeout: 258 seconds]
rohitksingh_ has joined ##openfpga
rohitksingh has quit [Ping timeout: 258 seconds]
rohitksingh_ has quit [Ping timeout: 258 seconds]
rohitksingh has joined ##openfpga
rohitksingh_ has joined ##openfpga
rohitksingh__ has joined ##openfpga
rohitksingh___ has joined ##openfpga
rohitksingh____ has joined ##openfpga
rohitksingh has quit [Ping timeout: 258 seconds]
rohitksingh_ has quit [Ping timeout: 258 seconds]
rohitksingh__ has quit [Ping timeout: 258 seconds]
rohitksingh___ has quit [Ping timeout: 258 seconds]
rohitksingh____ has quit [Ping timeout: 258 seconds]
rohitksingh_ has joined ##openfpga
rohitksingh_ has quit [Ping timeout: 258 seconds]
rohitksingh has joined ##openfpga
rohitksingh_ has joined ##openfpga
rohitksingh__ has joined ##openfpga
rohitksingh has quit [Ping timeout: 258 seconds]
duck2 has quit [Quit: The Lounge - https://thelounge.chat]
rohitksingh_ has quit [Ping timeout: 265 seconds]
duck2 has joined ##openfpga
rohitksingh__ has quit [Ping timeout: 265 seconds]
Asu` has quit [Remote host closed the connection]
ym has quit [Ping timeout: 260 seconds]
<rombik_su> ZirconiumX: Can you please explain this Quartus 'Pad view' to me? I'm looking at 5CEFA2F23 floorplan; there's a nice X (0-54) and Y (0-45) grid with various elements and stuff.
<rombik_su> For example: PIN_F3, PAD_291 (MSEL4), X4/Y45
<rombik_su> It's X3/Y45 on Pad view and X4/Y45 on Floorplan.
ym has joined ##openfpga
<rombik_su> Nevermind, looks like it's the actual wirebonding pads coordinates, they can be placed in adjacent grid tiles
<ZirconiumX> Yup
emeb_mac has joined ##openfpga