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<Xiretza>
I'm trying to use LiteDRAM in my design, and it does have this gen.py script to generate Verilog RTL, but it expects a YAML config file. does anyone know where I can get that?
<Xiretza>
ah, there's a few in examples/, shoulda looked there first. I was looking all over litex and litex-boards, but not there.
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<ZombieChicken>
.
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<Finde>
Xiretza: you may know already but there's also #litex which is pretty active if you're looking to solve problems
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<Xiretza>
Finde: ah, thanks!
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