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<pepijndevos>
wah... according to the schematic the Trenz uses a W74M64FVSSIQ, but the datasheet does not at all mention the commands, just saying they are "normal serial" and then goes on to document weird security features
<pepijndevos>
Also no mention of the HOLD and WP pins... am I even looking at the right datasheet...
<pepijndevos>
In [7]: flash.SerialFlashManager.get_flash_device("ftdi://ftdi:2232/2")
<pepijndevos>
Out[7]: <spiflash.serialflash.W25xFlashDevice at 0x7f9a500ce820>
<pepijndevos>
hurray
<trabucayre>
pepijndevos: with a custom proxy in the FPGA ?
<pepijndevos>
yea
<trabucayre>
cool
<pepijndevos>
if this works it'll be like a dozen lines of litex stuff to automatically push the binary.
<pepijndevos>
except so far chip erase is not working
<trabucayre>
due to secure ?
<pepijndevos>
dunno, no I think... I can erase sectors but chip erase just times out. Maybe it's just slow? How long is that stuff supposed to take?
<pepijndevos>
It times out after 11 seconds apparently
<pepijndevos>
oh, I just had to increase it. works now...
<trabucayre>
ok
<pepijndevos>
welp, once the ftdi is in spi mode, how do i get the tty back?
<trabucayre>
it's a problem with libftdi < 1.5. driver is detact but not reattach...
<trabucayre>
You need to unplug cable
<trabucayre>
for openFPGALoader I've rewrite close function to reattach ...
<pepijndevos>
ahhh I was wondering... with vendor tool I don't get tty back, but with yours I do
<pepijndevos>
huh, so what about libftdi 1.5? Usually arch is pretty cutting edge, but I have 1.4-4
<trabucayre>
with libftdi 1.5 if the lib has used detach when requiring device, at the end it call reattach
<trabucayre>
with the vendor tool it's a bit different. libft2xx don't know howto detach -> you need manually modprobe -r ftdi_sio
<pepijndevos>
I was sram programming, so bit inconvenient to replug haha, but whatever, just switched to flash, since I'm flashing the bios anyway.
<trabucayre>
ASAP i will add direct spi support
<trabucayre>
It's open the door to be ice40 compatible :)
<pepijndevos>
uh... when I pass to --write-flash to openFPGALoade it still says Flash SRAM
<pepijndevos>
and then SRAM Flash: FAIL
<pepijndevos>
Yea I don't need the SPI mode myself now, since I just used LiteX and PySPIFlash, but it would be a nice feature
<trabucayre>
for SRAM it's a typo ...
<trabucayre>
for fail can you provide full display ?
<pepijndevos>
yea but this time also it definitely did not actually work. bitstream is not activated
<trabucayre>
I need to find a way to use unittest with real hardware :)
<pepijndevos>
ahhhh, today is not my day... it's doing the 99% thing again for sram programming now
<pepijndevos>
last time we did just replug it right...
<pepijndevos>
reboot all the things...
<pepijndevos>
well that is at least back to normal...
<trabucayre>
pff :-(
<pepijndevos>
Does anyone have some purely hypothetical suggestions for how one would take a peek inside some encrypted IP? XD
<mwk>
pepijndevos: a simple idea is
<mwk>
run a simulation with it
<mwk>
Ctrl-\ the simulator when it's simulating to generate a core dump
<mwk>
look in the core dump for decrypted version
<pepijndevos>
haha nice
<mwk>
works better if you "fix" memory allocator by substituting free() with a function that does nothing
<mwk>
but also
<mwk>
what kind of encrypted IP is that?
<pepijndevos>
So Gowin has embedded SDRAM, right? But they only tell you how to use their IP, not anything about the SDRAM itself... which is a bit annoying if you want to use it in LiteX for example.
<mwk>
and the IP is some kind of high level interface with FIFOs and whatnot?
<mwk>
and you are sure it's not hardware IP?
<pepijndevos>
It has encrypted verilog, it's not just some primitive. Most likely it's a SiP where there is a whole SDRAM chip hooked up to some IOB. For PSRAM they actually give you the chip name of the thing they bonded in there, but not the pinout
<mwk>
even hardware IPs have verilog models
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<pepijndevos>
hmmm
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<pepijndevos>
I asked Gowin kindly and they said "That’s correct the memory is added using SIP and connects to the FPGA via one of it’s I/O banks, hence the ‘R’ version with SIP memory support less User I/O."
<pepijndevos>
It's a winbond device, but not clear which
<pepijndevos>
He'll have a look if there is any pinout info.
<pepijndevos>
That explains why GW1NR-9 pinout only shows 3 banks... I guess I could also synth an example with their IP and unpack the bitstream to see what goes where.
<omnitechnomancer>
pepijndevos: pretty much all spiflash uses the same command set, you can probably find it if you look in the linux kernel sources
<pepijndevos>
oh yea, spi flash works. current struggle is sdram
<omnitechnomancer>
I think the Anlogic is the same about not telling you which IOBs the dram it attached to (at least the pinout, the floor plan view will tell you which ones are SDRAM pins but not which pins they are but this could be used with a design using the IP block to pick out the pins I think)