marcan changed the topic of #asahi-dev to: Asahi Linux: porting Linux to Apple Silicon macs | General development | GitHub: https://alx.sh/g | Wiki: https://alx.sh/w | Logs: https://alx.sh/l/asahi-dev
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<kettenis> I extended the asahi linux device tree with the minimum nodes from the corellium device tree to bring up pcie
<kettenis> loading u-boot works and it runs the OpenBSD bootloader which in turn loads the OpenBSD kernel
<kettenis> unfortunately the kernel dies as the result of an SError exception as soon as it tries to exec init
<kettenis> ESR_EL1 doesn't seem to provide any hints here
<j`ey> kettenis: and it's not related to the ngnrne mode on pcie?
<kettenis> shouldn't be
<kettenis> I'd expect the SError to occur earlier if that was the case
<marcan> kettenis: corellium disable SError bus issues wholesale
<marcan> macos does not
<marcan> this tells me they are doing something wrong
<marcan> are you mapping the PCIe BARs as nGnRE?
<marcan> you want to print the apple bus exception related registers
<marcan> those will tell you what kind of fault happened
<marcan> ADR has the physical address (with some stuff in the top bits)
<kettenis> thanks, will do
<kettenis> thanks to m1n1 I can now easily switch between the correllium preloader and, erh, well m1n1 ;)
<marcan> :)
<marcan> fwiw, you can do msr((3, 3, 15, 8, 0), 0) with shell.py before chainloading u-boot
<marcan> that's what preloader does, which just shoves all those errors under the carpet
<marcan> but it might help confirm we're not dealing with something else here
<marcan> ah, but that won't do it for SMP secondaries
<marcan> though I think that one is per cluster
<marcan> if so you have a 50/50 chance depending on the cpu :)
<marcan> either way, let me know what values you get, I can do a quick experiment to confirm what they mean
<kettenis> still running only on the first core
<marcan> should work then
<kettenis> yup, that "fixes" it
<kettenis> will look at those IMPDEF registers
<kettenis> thanks for the hints
<marcan> np! let me know how it goes
<marcan> I'll take the chance to document those registers a bit more, now that I have more tools to experiment with
<kettenis> that'd be great
<kettenis> one issue I'm facing is that "TTY mode" doesn't seem to work for me
<kettenis> at least it doesn't show any serial output from u-boot and my kernel
<kettenis> could very well be that the miniterm implementation in the python serial module is broken on OpenBSD
<jannau> kettenis: serial console in uboot was working for me with u-boot a0de919efcd and trivial patches for the compatible strings, I think with miniterm
<kettenis> I'm talking about the python miniterm implementation here
<kettenis> if I use cu(4) I see the serial output
<kettenis> ah, looks like our exuart(4) driver is touching a register that it shouldn't
<kettenis> shouldn't be too difficult to fix
<kettenis> dinner first though
<kettenis> thanks again marcan
<kettenis> do you want the register values?
<marcan> might be useful, yeah
<marcan> I was just running some tests to update the docs
<jannau> I think I saw serial output from u-boot in python miniterm booted from m1n1
<kettenis> L2C_ERR_STS 0x11000ffc00000082
<kettenis> L2C_ERR_ADR 0x28000023520002c
<kettenis> L2C_ERR_INF 0x2
<kettenis> 0x235200000 is the physical address of the uart
<marcan> I *think* 82 means recursive fault, but maybe it doesn't
<marcan> L2C_ERR_INF 2 I'm not sure about
<marcan> the top bits in ADR are what I see for writes
<marcan> ah, I just repro'd
<marcan> I get that for 16-bit or 8-bit writes to that register
<marcan> 2C is UFRACVAL supposedly
<marcan> I think this bus interface only allows 32-bit writes
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<kettenis> so u-boot messes this up
<kettenis> it also doeas an 8-bit write to UTXH
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<kettenis> interesting that those writes trigger a SError but the written characters still appear on the serial line
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<kettenis> cpu7 at mainbus0 mpidr 10103: Apple Firestorm r1p1
<kettenis> cpu7: 192KB 64b/line 6-way L1 VIPT I-cache, 128KB 64b/line 8-way L1 D-cache
<kettenis> cpu7: 12288KB 128b/line 12-way L2 cache
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