<marcan>
of course those pins are going to get cropped off the bottom of the board, but well, that's accurate
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<whitequark>
yeah that's fine
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<marcan>
whitequark: think it's okay to pull in that (modified) footprint? we have a verbal OK from the owner, they just haven't added the license to the repo per se
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<whitequark>
mhhh
<whitequark>
i'd probably rather wait until the owner fixes the repo :S
<whitequark>
marcan: i'm actually not sure how to configure it
<whitequark>
anyway yes
<whitequark>
let's tag
<whitequark>
(they do not move)
<whitequark>
wait
<whitequark>
export design files first
<marcan>
ah
<marcan>
sure
<marcan>
let me do that after lunch then, I've got someone waiting here :-)
<marcan>
but I'm going to tweet the 3D renders
<whitequark>
sure
<esden>
Ohh interesting! I just saw in the 3d render that the 2pin connector is the other way around than the one I have. I found some 2pin headers with that latch turned the other way, so the latch is against the PCB. I thought that might prevent people from getting snagged on the tab. But I guess that does not matter much. Having the tab against the PCB might actually be bad as it will prevent the tab from bending outward.
<esden>
I need to test it. :)
<marcan>
esden: the polarity is designed with the tab outward (as was the case in revB); if we use the other ones we need to swap the pins on the board
<marcan>
(and then I just wasted my time doing that footprint :p)
<esden>
marcan: lol... ok :) (I almost felt like making a cheap joke about your time being not highly valued but that would not be true or very funny so we will just move on). I need to see if I have the one you have in the rendering then, or if I need to order them.
<esden>
I have the feeling that I ordered the other ones, and felt that they were the wrong ones and then ordered the ones with the PCB facing tab.
<esden>
So I actually might have the right ones already.
<esden>
YEY for all the connector options. >_<
<marcan>
yeeeah :p
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<_whitenotifier-3>
[GlasgowEmbedded/Glasgow] marcan pushed 1 commit to master [+0/-0/±1] https://git.io/fjZDS
<_whitenotifier-3>
[GlasgowEmbedded/Glasgow] marcan 5351475 - revC1: move via away from Sync
<marcan>
whitequark: nothing to see here :-)
<marcan>
(turns out when I moved that via away from G/S I moved it straight into Sync, and having a hole on top of that text would haunt me forever)
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<marcan>
(nobody will notice I changed that :p)
<marcan>
going to generate design files now
<marcan>
ah, a few things need nudging in the fab layers, will fix that (no impact to 3D for those)
<electronic_eel>
marcan: what kicad version are you using?
<electronic_eel>
I already updated to 5.1.2 a few days ago
<marcan>
yeah
<marcan>
it's fixed in 5.1.2
<marcan>
which isn't in portage yet :(
<marcan>
electronic_eel: can you print those out for me? I can't be arsed to cook an ebuild update just for this nonsense
<electronic_eel>
I'm using Fedora, they already have it packaged. I just had to recompile it for Fedora 29
<whitequark>
ahhh, linux
<electronic_eel>
marcan: what exactly do you want me to do?
<marcan>
grab latest git, then in pcbnew file->print, select only Edge.Cuts + F.CrtYd + F.Fab, all layers on single page, Fit to page, color, page setup: A4, any printer, landscape, and print to PDF
<marcan>
then do the same with Edge.Cuts + B.CrtYd + B.Fab
<marcan>
and send me both files
<marcan>
actually I wonder if Arch Linux has the new version
<marcan>
sec
<electronic_eel>
hmm, don't you go through svg & inkscape for printing from kicad?
<electronic_eel>
I always had much better experience when exporting to svg and creating pdfs from there
<marcan>
I mean I'm sure I could, but this works fine?
<marcan>
looks like arch linux has it
<marcan>
I'll just use that
<electronic_eel>
I've been doing it through svgs for years
<electronic_eel>
direct printing from kicad had bad rendering for me in the past, but svg was always fine
<electronic_eel>
don't know if they improved that, didn't try, I sticked to my used procedure
<marcan>
fair :)
<electronic_eel>
I'm off to lunch
<marcan>
lol, I just realized that mirrored output is broken (and was broken in revB already)
<marcan>
electronic_eel: you're right, svg export works better anyway
<marcan>
let's go with that
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<marcan>
ah, but inkscape can't "fit to page", meh
<marcan>
okay, you know what. PDF export from kicad, not mirrored, then import into inkscape the bfab layer, mirror, save as PDF again, mutool
<marcan>
this is stupid but whatever, I want this to be done :p
<_whitenotifier-3>
[GlasgowEmbedded/Glasgow] marcan pushed 1 commit to master [+0/-0/±1] https://git.io/fjZSY
<marcan>
ok, did a quick check on the DFN6 regulators and the ESD diode array, they look good
<marcan>
shipit!
<electronic_eel>
marcan: hmm, the fabrication.pdf, is that really still used today?
<electronic_eel>
I mean, finding the matching component to a text can be difficult in tight areas
<electronic_eel>
nearly the same as the silkscreen
<electronic_eel>
I now prefer to use the interactive html bom for this
<electronic_eel>
much easier to use and no mistakes matching text to actual component
<electronic_eel>
my local contract manufacturer loved it
<electronic_eel>
had never seen something nice like it
<electronic_eel>
an alternative would probably be boardview files
<electronic_eel>
hmm, just saw that there is someone named whitequark who published a kicad to boardview exporter ;)
<whitequark>
lol
<whitequark>
esden: ^^ you can take revC1 design files and run with them
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<sorear>
so the final decision was to keep J5 despite ESD concerns?
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<tnt>
I guess someone already thought of it, but chaining 2 * revC with the LVDS port on each and make them appear as one larger device would be neat :p
<electronic_eel>
either larger device or just as a second fx2 with buffering for more throughput to the pc
<electronic_eel>
sorear: I'd consider the lvds port as cold-plug and for careful handling
<electronic_eel>
but adding esd protection for lvds isn't that easy
<sorear>
yeah I'm just wondering what "careful handling" entails
<tnt>
sorear: if you're paranoid, buy a female connector, short all the pins and use that as a 'cap'.
<sorear>
kind of odd that the TPnn on the schematic don't match the silkscreen
<electronic_eel>
sorear: wear an esd wristband and use an esd mat, then you should be safe
<electronic_eel>
keep Glasgow in a case with access to the lvds port closed otherwise
<whitequark>
yes, that's the idea
<whitequark>
not have an opening on the case
<electronic_eel>
re testpoints: they are marked with text telling the user what they find there
<electronic_eel>
easier to use this way, you don't have to look it up in the schematics
<electronic_eel>
I think stuff like "3V3" or "SCL" is rather obvious and hard to confuse
<whitequark>
it is much harder to confuse than TPnn
<sorear>
yes, is much better, the weird part is that TPnn shows up on the schematic at all
<sorear>
how thing is the case at this point
<whitequark>
there's one case made fr laser cutting
<whitequark>
and another case designed by greg
<whitequark>
the former is in the repo
<whitequark>
the latter is sadly not but i'll make sure it gets in the repo some day
<whitequark>
greg's case is for 3d printing that is
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<sorear>
so if you have two boards connected via SYNC and plugged in, and for some reason the host is supplying Vbus to one board but not the other, the pullups on the powered board will lift 3V3 on the unpowered board, possibly leading to 3V3 > 5V0. that sounds bad?
<sorear>
or I should ask what am I missing
<whitequark>
it wouldn't get out of reset
<whitequark>
due to the voltage superviso
<whitequark>
r
<electronic_eel>
sounds indeed like an issue to me
<electronic_eel>
the 10k pullup (R44) won't allow much current, tough
<electronic_eel>
but still
<electronic_eel>
protecting the pullup with a diode would be a solution
<electronic_eel>
marcan: what do you think about this?
<electronic_eel>
the protection diode in the adc on the sense pin could act in a similar way
<electronic_eel>
(I mean the internal protection diode in the adc itself)
<sorear>
the maximum amount of injected current through two back to back R44s is 165 µA; D1 alone would sink a third of that
<electronic_eel>
I don't think we should strictly limit the sync to connections between Glasgows
<electronic_eel>
you could hook up a scope sync output or a reference clock or something like that there too
<electronic_eel>
then you'd have a push-pull on the other end
<sorear>
what does the "can be connected to 5V circuits directly" annotation mean?
<electronic_eel>
as long as the fx2 and fpga stay in reset (by the voltage supervisor) we won't have anything drawing enough current to discharge it
<electronic_eel>
if you connect a 5v pushpull to the sync, the 3v3 rail may even slowly rise above 3v3
<sorear>
well the fpga is mostly on the 1v2 rail
<electronic_eel>
ah, wait. the TV733 regulator has a body diode from out to in
<electronic_eel>
so the 5v rail will slowly rise too
<electronic_eel>
with the 150µF it will take ages, but still
<sorear>
to keep the 3v3 rail below 3v3 when a 5v device is attached, the ICs need to draw 114 µA in reset
<sorear>
"suspend current" for the -13A is given as 300 µA in the datasheet; I'm not sure what that means
<electronic_eel>
-13A?
<sorear>
CY7C68013A
<electronic_eel>
ah, the fx2
<electronic_eel>
not sure, could be reset or the special usb suspend condition
<electronic_eel>
I guess the latter
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<electronic_eel>
when the voltage supervisor begins to run (at least at 2.7v), it will pull down 3V3EN
<electronic_eel>
this will discharge the 3V3 rail
<sorear>
why would the voltage supervisor run
<electronic_eel>
making sure that it never can go above 3V3 by current injected
<electronic_eel>
sorear: because of the body diode in the 3v3 regulator
<electronic_eel>
it charges the 5v rail
<sorear>
mm
<electronic_eel>
so the 5v rail is at least one diode drop below 3v3
<sorear>
unclear what voltage 3v3 could get up to given the leakage of everything on it
<electronic_eel>
the new regulators claim to also discharge the output
<electronic_eel>
but I'm not sure if that works when the en is pulled low before the regulator did some regulation before
<electronic_eel>
I think it would be best if marcan could try that out with the new regulators
<electronic_eel>
even if wire wrapping them in will be a pain
<marcan>
honestly I think we're trying too hard here
<marcan>
all just for R44?
<marcan>
eeeh
<electronic_eel>
and the protection diodes in the adcs
<electronic_eel>
could you hook up a 10k to 5v and try to charge the 3V3 rail with it?
<sorear>
it'd be good to actually know how much leakage current the 3V3 rail can sink before anything reaches a dangerous voltage
<marcan>
those also have a 10K in front, plus a divider pulling that down
<electronic_eel>
I mean external 5V and having the Glasgow disconnected
<marcan>
yeah let me just dump 5V into a 10K into 3V3 and see what happens
<marcan>
I bet not much :p
<sorear>
D1 will light up
<electronic_eel>
the new regulators might behave differently than the MIC that is in revC0 though
<marcan>
0.7V.
<marcan>
D1 does not even remotely begin to light
<marcan>
look I'm not touching revC1 for this hypothetical problem :p
<marcan>
I highly doubt the new regulators are going to be much different in this regard
<electronic_eel>
ok, then there is enough on the 3v3 rail that is leaking the current away
<electronic_eel>
so then there is no problem, good to have verified that
<sorear>
huh, now I'm curious where the current is going
<sorear>
not gonna ask you to waste any time on it though
<electronic_eel>
at these voltage levels you won't find any info in the datasheets
<electronic_eel>
could be anything
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<marcan>
< sorear> what does the "can be connected to 5V circuits directly" annotation mean? <- fwiw we thought of the 5V -> 3V3 on the sync and dismissed it as a triviality, because injecting such a tiny current into the 3V3 rail would do nothing
<marcan>
(via the pullup)
<marcan>
we didn't think of the powered off case, but eh, as I expected it's not an issue :P
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