<emily>
and I try to keep the nixpkgs packages building on darwin
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<electronic_eel>
esden: I just found some more small nits - how come you know me better than myself?
<electronic_eel>
block diagram, i2c bus line above the upper settable power supply, there is a small break in the line
<electronic_eel>
block diagram, upper settable power supply block, the red power arrow leaving the power supply leaves at a different position than the one on the lower power supply. I think the arrow one the lower one looks better
<electronic_eel>
block diagram, black arrows between pullup/down and the GPIOs, the end of the arrow touches the "GPIO Fontend" block. I think it looks better if there is a small space between them like in the original diagram
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<esden>
I am calling it good and will update the page. I think remaining nitpick improvements will have to wait for the official campaign launch page. :D
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<electronic_eel>
esden: thank you for incorporating my improvement ideas, looking very good now
<tnt>
Did anyone use the jtag-svf applet to program an ecp5 ?
<whitequark>
yes
<whitequark>
works fine for me
<tnt>
And loading a svf should just load the 'runtime' config right ? ignoring whatever is in flash ?
<whitequark>
yes
<whitequark>
i think it may depend on the svf file actually
<whitequark>
but the default by ecppack should do that
<tnt>
Looks like the very last SDR fails.
<whitequark>
hm
<whitequark>
strange
<daveshah>
What is your ecppack command line
<tnt>
ecppack --svf out.svf --input test.config
<daveshah>
Seems fine - I know sometimes the chip gets unhappy with bitstreams with SPI flash commands (when setting mode or frequency) being sent over JTAG
<tnt>
I do get "W: g.applet.interface.jtag_svf: SVF: test vector did not reset DUT explicitly, resetting"
<tnt>
but ... not sure if that's an issue.
<daveshah>
Can you see what the last SDR does read?
<ktemkin>
in the case where the extra SPI flash commands makes it unhappy, it'll report that the bitstream "provides data past the device's SRAM array"in its status register
<tnt>
Is the meaning of the bits explained somewhere ?
<daveshah>
tnt: yes, in the sysCONFIG TN
<daveshah>
that looks like 9, 10, 11, 12 which means "not done; read and write enabled; configuration logic is busy" afaics
<daveshah>
maybe glasgow is just too fast...
<mwk>
glasgow being too fast has happend before
<tnt>
Arf I changed the pause at the end from 1ms to 1s and now it doesn't report any error ...
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<tnt>
Although I'm not sure my design is actually loaded, looks like it still loaded the flash one.
<tnt>
Arf no ... pebkak.
<tnt>
So I had programn defined in the top level but not assigned to anything (since it was just a blinky test). ysosy mapped it to default 1'b0. So when jtag loading was done, it was immediately rebooting to flash and I guess the jtag probe for 'done' was happening right during the flash reconfig.