01:33 <DX-MON> whitequark: question for you.. how do I go about simulating an applet I'm writing to debug the nMigen part? I'm struggling to get my logic right

01:35 <DX-MON> (anyone else who knows about this subject is free to jump in too)

13:01 <fest> DX-MON: this is what I do: https://linx.wot.lv/cmd1.py

13:02 <fest> I've split the nmigen modules of my applet in separate py files and I just execute them to run the simulated version

16:09 <fest> damn it, I give up

16:10 <fest> so, I've been trying to acquire data from a video sensor at 48MHz

16:12 <fest> I feed the sensor a clock (48MHz) and the sensor has two data lines, word size = 14 bits. I sample the inputs, combine 4/3 nibbles worth of data and write to fifo

16:14 <fest> https://linx.wot.lv/n2o81bhc.png d1 is clk, d4, d5 is sensor data lines, d10 is when I start sampling (the sensor starts outputting data some cycles after it has received a command), d13 is fifo w_en

16:15 <fest> at start of the line, sensor outputs a known pattern of data lines (0b11001100110011)

16:15 <fest> when I'm running the applet multiple times, I receive something similar to the pattern as the first two bytes

16:15 <fest> but sometimes it's shifted

16:16 <fest> sometimes one of the data lines is 0 instead of one

16:17 <fest> but every single time the latch, and w_en signals are correct - so the module is starting to sample and writing to fifo when it should be

16:17 <fest> yet the data is different

16:19 <fest> I've looked at the physical layer with a scope- although the data signals at glasgow connector are, ehm, damaged, the buffers clean the signal up nicely

16:20 <fest> I've made a loopback test applet, where I generate the same pattern on negedge and capture it on posedge- it works perfectly fine there

16:21 <fest> I am using FFSynchronizer on the input signals

16:22 <fest> I've added clock constraints on the input pins as I noticed that nextpnr says that it's annotating ports with timing budget of 12MHz (not sure it does anything)

16:26 <fest> if anyone cares to look at what I could be doing wrong, the design is here: https://linx.wot.lv/acq.py (ISC0901B0SHRAcq is the meat of it), https://linx.wot.lv/main1.py -data_in_fifo is fx2's fifo

16:26 <fest> timing is met at ~100Mhz

16:27 <fest> I feel like this will be something basic about the digital design

16:46 <fest> I guess I'll have to try freeing enough la channels for w_data to narrow the problem down

18:19 <DX-MON> thanks for the pointer fest - much appreciate that. I'll get to writing a pysim harness tonight then and feed in some data from one of my captures with the JTAG-analyzer applet I wrote to sim real state transitions in the JTAG-PDI one and see what comes out

19:53 <fest> re my problem: "oh, this is how FFSynchronizer works" :)

21:22 <modwizcode> oops :)