azonenberg changed the topic of #homecmos to: Homebrew CMOS and MEMS foundry design | Wiki: http://homecmos.drawersteak.com/wiki/Main_Page | Repository: http://code.google.com/p/homecmos/ | Logs: http://en.qi-hardware.com/homecmos-logs/
<nmz787_> promach: seems like a simple rule, at least for NAND gates, as shown on wikipedia
<nmz787_> 2n for static NAND, vs n+2 for dynamic
<nmz787_> (where n is transistor count)
<promach> how to directly relate equality comparison to high fan-in NOR ?
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<promach> nmz787_: hi
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<nmz787_> hi promach
<promach> how to directly relate equality comparison to high fan-in NOR ?
<nmz787_> my reasoning is less transistors for the number of bits you need to NOR, means less wires, means less constraints for routing those traces (fan in)
<nmz787_> reduces the 'ratsnest' in PCB terms
<promach> how is that "routing ratnest" related to equality comparison
<promach> ?
<nmz787_> it is related to fan-in
<promach> fan-in is how much input a gate can take, right ?
<nmz787_> and likely the structure of NOR in static, maybe cascaded or something... so I'd infer from that comment on the forum, that you have less delay with dynamic logic in this case
<nmz787_> as far as I understand, fan-in is the opposite of fan-out
<promach> faster with dynamic logic
<promach> fan-out is how much output a gate can drive
<nmz787_> I don't think that is correct
<nmz787_> pretty sure fan-out == break-out
<nmz787_> sure a given transistor has some drive strength, but in this case I didn't consider that
<promach> inst.cs.berkeley.edu/~ee40/su06/lectures/lecture16.pdf
<nmz787_> having more wires would mean more capacitance
<nmz787_> which increases lag
<promach> nmz787: I still do not get how high fan-in NOR gate is related to dynamic logic
<nmz787_> as I said, the number of inputs scale with different equations
<nmz787_> so your capacitance also will follow, since each input has a trace associated, and every trace adds capacitance
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