04:45 <promach> why RAM has large clock-to-output delays ?

04:47 <promach> let's say the clock line is WL in the 6-transistor memory cell as in https://en.wikipedia.org/wiki/Random-access_memory#Types_of_random-access_memory

05:21 <promach> does the large the clk-to-q delay have to do with https://inst.eecs.berkeley.edu/~cs250/sp17/lectures/lec07-memory-sp17.pdf#page=21 ?

05:51 <wallacoloo> promach: My understanding is that the large clk-to-q is due to all the capacitance hanging of the bit line (wire cap + the drain of all the other cells on that line), plus that the devices are small and have low drive strength. So high RC = long clk-to-q.

05:52 <wallacoloo> But DRAMs use sense amplifiers, and I'm not sure what limits those.