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<
SolidHal >
Has anyone had issues with 5.2 black-screening on veyron-speedy (asus c201)? I don't get any output on serial even with earlyprintk.
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urjaman >
also i think i've seen your stuff on github, hi :P
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micken >
In VOP (rk3399) dsp_ctrl1 , which bits are valid (starting at 20) for positvie pol vsync negative hsync, "10"?
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dj_sundog >
hello party people - any chance anyone has a working linux image for an rk3318-based board lying around?
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micken >
is there a good reason why leave out VOP docs from trm's on rk3399 and leave out HDMI from rk3288 trm's
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mmind00 >
micken: hdmi is from designware, and I guess they don't want to have it public
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micken >
but the docs for rk3399 includes hdmi
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<
micken >
even som notions about phy
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micken >
other vendors have more or less complete docs
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micken >
I am basing rk3* driver on our i.MX6 one
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micken >
Most code are the same, except for some phyconfig
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micken >
But because of all this, I wonder what the exact difference is between rk3399 vop and rk3288. I think I have the polarity right in dsp_ctrl1 , but for the other bits I stumble in the dark.
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<
micken >
linux on my rockpro64 sets dsp_ctrl1 to 0x00907801 , where the "9" is polarity bits
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micken >
default reset is e400
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<
micken >
i didnt touch that register at all on rk3288
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