<ysculo>
I have NAND corruption issues with my A13 devices. mripard told me it was a known problem. I don't recall which NAND referencies were known to cause problems. Does someone have any information on that matter ?
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<ddc>
u can dd u-boot to ur sd and use mmc spl
<ddc>
this if you want to test the nand driver while booting from mmc
<scream_>
yes, it will be better for first test
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<ddc>
I've not tried this but u can simply change the spl boot function to return BOOT_DEVICE_MMC1
<ddc>
then just dd your u-boot +spl file to ur sd
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<ddc>
scream_: CONFIG_ENV_IS_IN_NAND and CONFIG_ENV_IS_IN_MMC needs to be adjusted according to your setup
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<scream_>
i have tried to change it in board.c
<scream_>
now it gives me ### ERROR ### Please RESET the board ### after the spl prompt
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<ssvb>
other than that, looks like it has a single channel memory configuration, based on the bits from SDR_COM_CR
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<libv>
720MHz is not unseen for ddr3
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<ssvb>
libv: DDR3-1600?
<libv>
not sure, but my odroid is supposed to be running at 800/880MHz
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<ssvb>
libv: the Exynos4412 user manual says "2x32 DRAM port" "x32 data bus up to 800 Mbps/pin", this sounds like a data transfer rate
<libv>
ah, ok, so it is already doubled
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<libv>
ssvb: you should really do a meminfo with the code that's on the ml btw
<libv>
where mripard contest the sun10i naming
<libv>
contested even
<ssvb>
libv: do you have it is some git repository?
<ssvb>
s/is/in
<libv>
not a public one, no, i intended to push it shortly after and never did
<ssvb>
ok
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<mripard>
libv: contest was accurate. I still do
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<ssvb>
libv: anyway, should we finally create a sun6i dram controller registers guide in the wiki?
<wens>
ssvb: assuming they did a good job designing the board and testing, i don't see why not?
<ssvb>
libv: yes, I know what you would reply :)
<wens>
ssvb: there is a "mbus" driver in the a80 sdk, under drivers/bus
<wens>
which i think is for DRAM_COM
<wens>
copyright not transferable/assignable in France?
<libv>
mripard: i asked a few times what you would name it instead
<libv>
mripard: i do not think i have seen an actual answer to that.
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<wens>
systemd author denoucing the kernel community in a g+ post... what's that about
<mripard>
libv: not on the ml then. And I repeatedly asked for sun8i-a33 (or whatever casing you might want)
<mripard>
wens: yeah, actually the copyright is split in two rights in france
<mripard>
wens: the moral right, and the "estate" right
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<mripard>
the moral right is possessed by the author, forever, and can't be transferred
<mripard>
the estate right is about who has the right to benefit from the work
<wens>
ah yes, we have that too :)
<mripard>
this one can be transferred, and is only valid for a number of years, before falling into public domain
<libv>
mripard: that is not used by allwinner either.
<libv>
sun8iw5p1
<mripard>
libv: that's not true
<mripard>
well
<mripard>
if you want to go for that, I'm fine with it then
<libv>
ok.
<ssvb>
libv: for the meminfo tool, just dumping the version id register value would be the best
<mripard>
wens: so you can't depossess someone from the fact that he is the original author, but you can depossess him from the right to benefit from it
<mripard>
wens: anyway :)
<ssvb>
libv: because, you know, it can't be arbitrarily renamed after the silicon is out and no pointless debates are possible ;-)
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<wens>
mripard: only way you can benefit directly from copyright on the kernel is if you relicense it i suppose
<libv>
ssvb: check the patches.
<libv>
and i did suggest AW<chip id>
<libv>
in accordance with my via unichrome work of yore
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<ssvb>
who needs the "sun10i" name then?
<libv>
ssvb: read the thread
<ssvb>
I have read it, a long time ago
<ssvb>
imho the "sun10i" thing is a red herring, just drop it for now and nobody is going to miss it
<libv>
no, it is not
<libv>
i wanted to avoid the pain of switching to aw<chip id>
<libv>
now we will have no other option but to do so when the next gen of ARM core, or the next baseless marketing rename happens
<ssvb>
come on, meminfo is just a small simple tool
<ssvb>
what kind of pain are you talking about?
<wens>
probably the kernel
<mnemoc>
all the compatible-with entries
<ssvb>
well, it's mripard's pain, why should *we* care? ;-)
<ssvb>
I mean, I just don't think that mripard really needs any assistance on this matter
* ssvb
is fine with just any name, as long as it is unique and does not need to be changed in the future
<libv>
ssvb: see, the second part of that sentence is exactly the problem
<mripard>
especially since I won't do any of the compatible renaming
<libv>
but nvm, it's pointless timewasting having such discussions to begin with.
<libv>
just like the simplefb nonsense.
<libv>
if it weren't such a huge misnomer, and such a trivial change, people wouldn't have cared
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<ssvb>
libv: maybe it makes sense to push all the meminfo changes, except the controversial sun10i part?
<libv>
sun8iw5p1 is what it will be named.
<libv>
but in a bit, i have to do some chores.
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<castor3>
Hi
<castor3>
My Olimex LIME is compiled with the armhf architecture, I wanted to know if it's possible to install armef packages on it
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<castor3>
(I don't if my "Hi" passed through my client, so "Hi! :)")
<libv>
why would you want to install armel packages?
<castor3>
The nginx repository doesn't have armhf packages, only armef
<libv>
build the packages.
<castor3>
Okay :D
<libv>
armel btw.
<castor3>
It wouldn't work?
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<castor3>
Yeah, armel. Sorry for the typo.
<libv>
why would the distinction exist this clearly?
<castor3>
i386/amd64 exist this clearly
<castor3>
I wait for the "..." you're giving me since last time
<libv>
doesn't that go down all the way to the libc?
<castor3>
It does. But maybe there's a multilib repo I can use, etc.
<castor3>
Well, anyway, I'll use the armhf version from the Debian repo... Thanks anyway ;)
<libv>
that's not done, as we are on low powered hardware
<castor3>
Okay
<castor3>
No problem with that. I wanted to state that I solved my former problem (the SATA boot stuff), but with a debian rootfs
<libv>
oh, you figured it out without a uart?
<castor3>
By compiling my own kernel, activating the SATA monolitically. It wouldn't work with an archlinuxarm rootfs, but I don't know why since I couldn't find an uart cable on saturday.
<libv>
you should still order one, you might run into similar issues again
<castor3>
libv: I didn't figure it out the way I'd have wanted: with an arch rootfs.
<castor3>
Yeah, i know, I'm going to order one
<castor3>
Now that I could manage to boot on debian and configure it a little, I can wait a weed to have my cable :D
<castor3>
week*
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<WarheadsSE>
Once you do have it, let me know what you find castor3 . I don't have a LIME, as I said, to test.
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<castor3>
Yep, no problem :)
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<johanbr>
Hmm. As soon as there's heavy network activity, the network drops completely on my pcduino 3 nano. ethtool prints
<johanbr>
version: SUNXI GMAC driver V0.1
<johanbr>
... which doesn't exactly inspire confidence. is this version known to be buggy?
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<johanbr>
forcing the port to 100 Mbit/s seems to get rid of the drops, but http transfer speed drops to 30 Kbytes/s
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<mnemoc>
test setting the cpu governor to performance
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<johanbr>
mnemoc: no cpufreq built into the kernel :(
<johanbr>
but I guess the CPU should be going full throttle
<slapin>
hi, all!
<slapin>
mripard: hi
<slapin>
mripard: I see arch/arm/mach-{mediatek,rockchip} but can't find anything related to Allwinner SoCs, please tell me where to look?
* slapin
looks at mainline git
<slapin>
ah, found it
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<slapin>
mripard: sorry, to much guinness and too little brain :(
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<hno>
hi slapin
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<hno>
Oh, A80 u-boot sources contains full flash & sd programmer code for flashing an image, including decryption.
<ssvb>
hno: very nice
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<ssvb>
hno: is the power management chip still using an openrisc core?
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<ssvb>
hno: anything interesting there after decryption?
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<hno>
ssvb, the management chip seems to be an ARM M3 this time.
<hno>
And there is not much interesting in Allwinner image files. All files packed in an image is in the SDK.
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<ssvb>
hno: I see, it looks like they used openrisc earlier in order not to pay licensing fee, but now went with the "mainstream" solution
<hno>
no idea on their reasoning. But my guess is that ARM could provide them with an M3 core block that uses less power than their own OpenRISC synthesis,
<hno>
and that they likely got that almost for free with their expanded ARM license.
<hno>
And it also looks like the M3 core is used kind of like a audio DSP during normal operations.
<hno>
But very little is known on it. All code is in a blob, and no header files except for message passing interface. + a large encrypted blob possibly loaded on the M3 by the bootloader.
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<hno>
as in not sure if he had to patch the sdk u-boot for it to be able to boot mainline kernel, or if the sdk u-boot has sufficient support for loading a dt.