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<wens>
hor63: logs?
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<smaeul>
mystery solved :) Allwinner is using GCC 3.4.4 to compile their ARISC firmware
<smaeul>
as in, the original port of GCC to "or32-uclinux"
<smaeul>
it actually makes my code noticeably smaller than or1k-gcc 5.4, because this version can omit function prologue and epilogue for leaf functions (or1k uses an lr like arm)
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<icenowy[m]>
smaeul: interesting GCC3.4.4 generates smaller code than 5.4?
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<anarsoul>
jernej: your HDMI patches do not work after rebased on linux-master :\
<anarsoul>
jernej: drm_of_find_possible_crtcs() returns 0 and as result sun8i_dw_hdmi_bind() keeps returning -EPROBE_DEFER
<icenowy[m]>
I think this is expected
<anarsoul>
icenowy[m]: expected that it doesn't work?
<icenowy[m]>
yes
<anarsoul>
why?
<icenowy[m]>
mripard changed the way TCON is set up
<anarsoul>
icenowy[m]: I saw, but I didn't expect it to break HDMI patches :\
<anarsoul>
icenowy[m]: are there any fixes or I should look into it?
<icenowy[m]>
jernej may want to fix it.
<icenowy[m]>
P.S. I'm playing with the new toy TL Lim gave me -- Pine H6 ;-)
<anarsoul>
cool
<anarsoul>
OK, how do I debug what's missing in display pipeline?
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<anarsoul>
icenowy[m]: btw, ethernet isn't working for me on pine64-lts neither in 4.14 with your patch to revert some changes nor in 4.15-prerc1
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<anarsoul>
icenowy[m]: hm, I made the same changes to drivers/gpu/drm/sun4i/sun8i_dw_hdmi.c as mripard made in 45e88f994add84d8cd3864d36064ea1ed1b08cdf and in 5b8f09100d6c85c4a8049a830b57f199b5b08278, yet it doesn't work
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<wens>
jernej: with both chains, does it still probe or not?
<jernej>
I didn't try it, since I develop everything on H3, where TV is not yet supported.
<wens>
well if all the components are enabled, and there are no unsupported encoders (like TV output), it should still probe
<jernej>
IIRC if you hardcode TCON0 input to mixer0 and TCON1 input to mixer1, it should work
<jernej>
TCON/mixer relationship switching isn't supported anyway, so you shouldn't lose anything
<jernej>
but as I said, I didn't experiment with that for some time
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<anarsoul>
OK, anyone got ethernet working on A64 in linux-next?
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<wens>
works for me
<anarsoul>
wens: for me it either complains on ifconfig eth0 up: 'platform 1c30000.ethernet eth0: stmmac_open: Cannot attach to PHY (error: -19)' or crashes https://dpaste.de/ESQy/raw
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<anarsoul>
wens: which board?
<wens>
bpi-m64
<wens>
building latest linus tree to verify
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<anarsoul>
wens: I think it's not working because dc1sw is disabled.
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<anarsoul>
wens: yep, renamed 'vcc-phy' regulator to 'phy' and now it works
<anarsoul>
I hope I get some time this weekend to clean up and prepare for submission A64 sound patches
<anarsoul>
codekipp1r: do you have any plans to submit your A64 sound patches? (you did most of the work) If no - I'll clean them up and submit soon
<wens>
it's ok to pick up other's work, as long as you keep the original author and SoB tags
<wens>
yup, emac works fine on linus' tree
<montjoie>
and on linux-next :)
<anarsoul>
wens: I suppose your bootloader enables dc1sw for you?
<wens>
according to icenowy[m] or montjoie, ATF does that
<montjoie>
wens: I sent the patch "arm64: allwinner: a64: add Ethernet PHY regulator for several boards" for that
<montjoie>
oups I acked
<icenowy[m]>
booted a U-Boot 2017.11 on Pine H64 via FEL ;-)
<wens>
yeah, it's not in my tree, but it still works, and dc1sw doesn't get turned off, kind of weird
<icenowy[m]>
(to init DRAM currently I'm using a hacked boot0)
<wens>
something is off
<icenowy[m]>
I think I might clean up the code and submit the patches?
<icenowy[m]>
writing struct sunxi_ccm_reg for a re-designed CCU is a disaster
<icenowy[m]>
and as the source of ATF on H6 is not opened yet, now I still cannot use PSCI and SMP
<icenowy[m]>
and directly reset64'ed to 0x4a000000 (U-Boot)
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<wens>
montjoie: have to used u-boot emac recently?
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<montjoie>
wens: yes on pine64 or bpi64
<montjoie>
I am setting my own LAVA lab, so tftp (via uboot emac) is the main way of test
<wens>
argh... something feels broken for my h3 boards
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<wens>
montjoie: can you try it on an h3 board with internal phy?
<rellla>
jernej: nice to see your DE2 efforts :) trying to push for 4.16 sounds great
<montjoie>
wens: yes
<wens>
on mine, it seems either the PHY is not doing auto-neg properly, not reporting the negotiated link speed/duplex properly, or something
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<wens>
the EMAC register is set to 1000 mbps half duplex, which doesn't make sense
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<montjoie>
on next-20171018 at least it worked!
<wens>
montjoie: argh, I meant U-boot, sorry
<wens>
it works fine under linux
<wens>
nevermind
* wens
feels stupid
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<montjoie>
wens: will try uboot also
<wens>
montjoie: I just did, and it seems to work well
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<wens>
I don't know what I did wrong in my previous attempts
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<Pe3ucTop>
Hello to all, could someone help to configure sun6i RTC to get 32khz output from CPU ?? I have defined RTC in DT but there is no clocks defined, how to apply those ? How to select internal/external clock as source ?
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<Pe3ucTop>
wens ? sorry, could you comment anything on RTC ?
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<Pe3ucTop>
I notices in most dtsi files the register length is ~ 0x54 but, in fact on V3s it should be around 0x200 or do this memory is dedicated to something else ??
<Ixnus>
smaeul: , junnie: fyi, apritzel: you've said that you burned the secure bit on one of your a64 boards, maybe you can dump the BROM ?
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<codekipp1r>
anarsoul: I've not been able to get them working on my pine64 and now it's stopped booting
<icenowy[m]>
it needs to be loaded by FEL after using something to initialize DRAM
<icenowy[m]>
currently the "something" I used is a hacked boot0
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<codekipp1r>
anarsoul: can you diff between your working setup and say my sunxi-wip branch to see if I'm missing something
<codekipp1r>
but ultimately if you want to push then sure go ahead....I tend to sit on things far too long
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<Pe3ucTop>
Do anyone know how to get sun6i RTC to work from external crystal at least ?? Currently it's working from internal osc .. :(
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<mripard>
Pe3ucTop: since 4.11 it should always be clocked from the external crystal
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<Pe3ucTop>
mripard: :D I'm using 4.13 , I see in driver it's "selected" = (wrong way) and this selection do not work. From register readout see that source is still Internal. An by changing register by hand to external osc stops clock counting.
<Pe3ucTop>
I do it on V3s , as well I would like to select output Gating, it doesn not affect at all..
<mripard>
Pe3ucTop: what do you mean by "it's "selected" = (wrong way)"
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<Pe3ucTop>
mripard: In 3.4 driver , to switch clock source AUTO_SWITCH is going disabled and then applied BIT(15) which is undocumented just comment "Fixup auto switch BUG, when powerdow" and then clock could be changed.
<Pe3ucTop>
I do not see anything similar in 4.13. Also in 3.14 is check for result. On V3s changing clock without Bit(15) do to take effect at all.
<mripard>
Pe3ucTop: then feel free to send a patch to fix this for v3s :)
<Pe3ucTop>
mripard: Probably will do it, but firstly I need to check that it will work :) , so Question is if 32768hz crystal selected by hand, do it must work out off the box? because when I select it, clock stops, no signal on crystal pins (checked by oscilloscope).
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<mripard>
what signal did you probe with your scope ?
<Pe3ucTop>
mripard: X32KOUT which drives crystal work. I check X32KIN too.. both do not have any signal.
<Pe3ucTop>
X32KOUT is always high , X32KIN is low.
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<icenowy[m]>
The name of the opi lite upgradation is called opi-lite2
<icenowy[m]>
and opi one upgradation is called opi-one plus
<icenowy[m]>
according to steven
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<mripard>
Pe3ucTop: iirc you need to enable the clock output
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<icenowy[m]>
The SPI0 controller of H6 adds dual/quad mode
<Pe3ucTop>
about SPI0 why current sun6i spi do not use DUAL mode ??
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<Pe3ucTop>
it's available in hardware..
<Pe3ucTop>
only DUAL receive mode, but still.
<tkaiser>
icenowy[m]: Wonderful names (again)
<icenowy[m]>
;-)
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<KotCzarny>
i miss the glorious pc times when specs of machines were in the names
<icenowy[m]>
this kind of names are not attractive to computer newbies ;-)
* KotCzarny
imagines how 'development boards' and 'newbies' fit together ;)
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<tkaiser>
Newbies (not so) surprisingly already fail to differentiate between Orange Pi PC Plus and 'Plus' :)
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<lvrp16>
orange plus hell
<icenowy[m]>
converting user manual to code is a hell...
<icenowy[m]>
I hate it
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<tkaiser>
icenowy[m]: BTW: did you further investigate about the additional led on OPi R1? I'm also wondering whether there's a GPIO to toggle power for the RTL8152 on the board?
<icenowy[m]>
no I didn't
<tkaiser>
But you could ask Steven if you would? ;)
<icenowy[m]>
don't forget that it's my friend's
<tkaiser>
s/would/want/
<icenowy[m]>
I don't care it ;-)
<icenowy[m]>
and I'm now playing with H6
<wens>
icenowy[m]: welcome to the club :) # 22:00 < icenowy[m]> converting user manual to code is a hell...
<icenowy[m]>
wens: I'm already in it ;-)
<icenowy[m]>
although I haven't done this kind of things for several months, since R40 CCU driver is made
<wens>
lol
<icenowy[m]>
and when suiting the new CCU of H6 in U-Boot... I grabbed a calculator ;-)
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<icenowy[m]>
their's many holes
<icenowy[m]>
tkaiser: steven claims opi lite2 and 1+ will be available in this year
<icenowy[m]>
but they're not so suprising -- no PCIE ;-)
<tkaiser>
Well, we need an OPi Lite 2 Plus Minus then (the one with mPCIe on the back)
<icenowy[m]>
P.S. I don't know whether "this year" means Gregorian year or Chinese year
<wens>
mostly means gregorian in modern contexts?
<icenowy[m]>
I think so
<icenowy[m]>
but hardware production in China is affected by Chinese new year
<icenowy[m]>
the Gregorian new year is only a plain small holiday usually, but the Chinese new year is a big one;-)
<icenowy[m]>
legally the former is 1 day and the latter is 7 days
<icenowy[m]>
but usually employers make the Chinese new year holiday much longer
<wens>
I don't like Chinese new year
<tkaiser>
Will there be any software usable 'this year' (be it Dec 2017 or Feb 2018)? At least the H5 BSP was quite a mess...
<wens>
tkaiser: isn't it always?
<tkaiser>
wens: You're right. But one year earlier with the A64 BSP people were at least excited and jumped into. Never happened with the H5 variant.
<tkaiser>
But on the other hand mainline support for H5 was done so fast that it really made no sense to touch the BSP mess :)
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<icenowy[m]>
I think H6 mainline won't be so easy
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<shadeslayer>
icenowy[m]: I was wondering what the status of DRM was on the pinebook and where I could find the latest stuff?
<icenowy[m]>
shadeslayer: still heavily out-of-tree
<icenowy[m]>
I can make no promise now
<shadeslayer>
icenowy[m]: ah damn, I thought the idea was to have mainline by Jan
<icenowy[m]>
you can use out-of-tree patches
<shadeslayer>
can you point me to a git repo instead?
<shadeslayer>
icenowy[m]: and well, before I try them out, what works and what doesn't?
<tkaiser>
lvrp16: Part of budget cooling so it depends ;) When I had a look with BSP kernel recently there were sysfs nodes and the clockspeeds there pretty low