<pmpp>
on mainline H5 cpufreq is fully supported i don't know for H3 i still run legacy which supports it
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<icenowy[m]>
montjoie, mripard: can I change the EMAC compatible string on V3s from sun8i-v3s-emac to sun8i-v3-emac?
<icenowy[m]>
the V3s chip ignored the PD GPIO bank on the die, which has full MII/RGMII interface
<icenowy[m]>
but V3 has it
<icenowy[m]>
the compatible string is not used in any device tree mainlined now
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<icenowy[m]>
or maybe I should just drop it and use H3 compatible? (as the EMAC part is equal on V3/H3)
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<icenowy[m]>
(and V3s just didn't wire out PD bank
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<dddddd>
anarsoul, icenowy[m]. Thanks for your advice some days ago (the 21th), about TERES-I and powering-up the LCD in ATF. I have it on!
<dddddd>
Power UP sequency (from Olimex schematics): Set eDP_RESET to LOW; Set DLDO3 to 1.2V; Set DLDO2 to 2.5V; up DLDO2; 2 ms delay; up DLDO3; 10ms delay; eDP_RESET to HIGH
<dddddd>
I hacked a bit the delays (with NOTICE()) because I don't know how to do it right. Any recomendation on how to sleep/wait in ATF?
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<embed-3d>
igraltist: pmpp: when I remember it right H3 has some problem with its nkmp clock, where the multiplier is applied before the divisor. This results in instability (in some cases the freq, gets first higher and then it goes down)
<embed-3d>
But I'm working on this
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<embed-3d>
H5 should also not support dvfs right now.
<montjoie>
icenowy[m]: if the copatible isnt used, go!
<BenG83>
embed-3d, I can help testing things on A64 boards
<BenG83>
I have a couple :)
<BenG83>
or H5
<embed-3d>
GenG83: What do you like to test? The ths stuff?
<BenG83>
yes
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<embed-3d>
Thanks for your offer! Right now there is noting to test for A64 and H5, since it is not ready right now. The next 1,5 weeks I will make a break on working on those things, since I have to learn for exams.
<embed-3d>
But I have a few THS patches that need testing on A80. Does sombody has an A80 Device and could test those during the next 1,5 weeks?
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<embed-3d>
I need to know if the interrupt timing looks ok (top commit is required) and if the temperature value looks valid (top commit sould be removed).
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<megi>
embed-3d: that problem with CPUX clock instability is well defined and already fixed, no need to repeat the effort
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<megi>
M=0 always, P>0 only for freq > 288HMz and there will be no stability issues
<embed-3d>
just found your git a few minutes ago! I had the same idea.
<megi>
:)
<embed-3d>
but it isn't mainlined yet?
<megi>
mainline has some PLL restart patches
<megi>
those should fix the issue too, but I haven't tested it
<megi>
trouble with NKMP factor selection fix is that it would be hard to distribute the resulting kernel, because u-boot needs to be patched too with the same fix
<megi>
otherwise you'll get lockups during boot on first frequency change if you're unlucky
<megi>
personally I can use the correct u-boot and linux combo and void the issue entirely, but I can't assume this for mainline kernel, thus I don't try to mainline these patches anymore
<megi>
s/void/avoid/
<embed-3d>
hmm ok
<embed-3d>
are you working on dvfs patches for h3/h5?
<megi>
though, it is definitely nicer to never lockup the NKMP clock by proper factor selection, instead of locking it up and restarting it
<megi>
I'm not trying to mainline them, if that's what you're asking for
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<embed-3d>
ok thanks!
<megi>
There's not much to work on, though, most of the work is DT configuration and thermal sensor driver + SY8106A driver for orange pi pc like boards
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<megi>
I'm glad you're working on the THS part for mainline, do you have your patches somewhere in git? I will try to integrate them, and give them a run.
<megi>
I like JMS578 based USB3/SATA, it seems to work well. Though I use it in a bit unusual cable setup.
<BenG83>
the JMS also have upgradable firmware
<BenG83>
I only use JMS567 or 578 now
<megi>
I provide power myself to the drive from a good 5V power supply and connect the SATA bridge to the drive via SATA extension cable, therfore I don't use the USB power supply to supply the drive, just the bridge.
<embed-3d>
I see more chances in the PCIE. Pcie with a sata adapter/transreciever can speed this thing up!
<BenG83>
yeah sadly the differential pairs are crossed wrong on my PineH6 prototype board
<BenG83>
but I think Tl will bring new board to FOSDEM
<embed-3d>
Yes, they will get new boards next week
<BenG83>
not sure if a single PCIe 2.0 lane with SATA will be much faster than USB3
<embed-3d>
5.0 Gbps says the datasheet
<BenG83>
I think they mean 5GT/s
<BenG83>
and with 8b/10b encoding that boils down to 500MB/s raw data rate
<BenG83>
with the additional layers that might boil down about to the same 400MB/s you can get from USB3
<megi>
also, minipcie/sata bridges are not that cheap, the cheapest I found is ~$14