#linux-sunxi on 2020-02-04 — irc logs at freenode.irclog.whitequark.org

2018-08-03 10:18 rellla changed the topic of #linux-sunxi to: Allwinner/sunxi /development discussion - did you try looking at our wiki? https://linux-sunxi.org - Don't ask to ask. Just ask and wait! - https://github.com/linux-sunxi/ - Logs at http://irclog.whitequark.org/linux-sunxi - *only registered users can talk*

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03:03 <wens> dcache enabled?

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04:40 <grey-bit> Thanks montjoie, that would be helpful

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05:07 <megi> enabling dcache slows down writes to 17MiB/s too

05:07 <megi> though DMA is fast, it's just on the CPU side

05:10 <anarsoul> megi: something's up with CPU clock? or some bus clock?

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05:47 <megi> maybe, but it's just one direction, with the same setup it can write at 300MiB/s and more if I'd rise the clock from 800 to 1.15GHz linux uses

05:47 <megi> I mean CPU can write that fast

05:48 <megi> it just reads very slowly

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06:17 <montjoie> grey-bit: the night made me remember, due to crypto API contrainst, the useability is very low, cryptoAPI need that you always have the intermediate hash between update()

06:17 <montjoie> so basicly you will have shaxxx accelerated only if size % 64

06:18 <montjoie> any other size will have lot of cpu wasted for handling the remaining buffer (and incresed complexity so bugs...)

06:19 <montjoie> but let's try a simple version which fallback on all non modulo 64 size andd see what happens

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15:48 <martinayotte> Anybody knows why H6 doesn't have any /sys/class/gpio/gpioX/edge while H3 and H6 have them ?

15:49 <fALSO> youre saying that H6 doesnt have it and has it at the same time

15:49 <KotCzarny> he meant 'h3 and h5'

15:49 <fALSO> ;-P

15:49 <fALSO> H6 support is a bit green i think

15:49 <KotCzarny> i bet that h6 has different gpio/irq engine

15:49 <martinayotte> Right ... s/H3 and H6/H3 and H5/

15:50 <KotCzarny> so either missing edge trigger entirely or not implemented

15:51 <martinayotte> it seems not implemented, but it shares the same code, except the tables ...

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15:54 <jernej> martinayotte: which port?

15:55 <jernej> H6 has interrupts on port F, G, H, L and M according to manual

15:57 <jernej> H3 has them on port A, G and L

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15:57 <jernej> and H5 on port A, F, G and L

15:59 <martinayotte> I didn't know it was port specific ... I will check again

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16:01 <martinayotte> jernej: thanks for the hint, it is present on F port

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16:02 <mru> the allwinner pinmux is annoyingly inflexible

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16:08 <ElBarto> jernej: H5 doesn't have them on port F, check the logs from ~2/3 weeks ago when I talked about it

16:09 <jernej> well, I just looked in manual

16:09 <ElBarto> yup I know

16:09 <ElBarto> they are present in the manual but not in hardware

16:10 <KotCzarny> or present, just not working

16:10 <KotCzarny> ;)

16:10 <jernej> anyway, it was just for ilustration that different SoCs support interrupts on different ports

16:10 <ElBarto> no, the offset for interrupts register are the ones for port G

16:18 <martinayotte> GIC table of H6 shows also the B port ;-P

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22:58 <tuxd3v> it redirects to https

22:58 <tuxd3v> sorry guys, wrong chanel

22:58 <tuxd3v> :S

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