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<MoeIcenowy>
Allwinner D1 is finally officially announced.
<wens>
MoeIcenowy: you get one?
<MoeIcenowy>
nope
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<gediz0x539>
good news
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<suprothunderbolt>
not sure if I've found a bug with sun4i-i2s... the docs for the a64 appear to suggest only 1-4 channels decode from TDM but the code suggest 1-8. Anyone know if >4 channel is possible?
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<buZz>
if maxime says its 8 , its probably 8
<buZz>
suprothunderbolt: maybe docs talk about stereo channels?
<suprothunderbolt>
maybe...
<suprothunderbolt>
DA_TXCHMAP looks the most interesting,
<suprothunderbolt>
says: 1xx: Reserved
<suprothunderbolt>
but default value is Default Value: 0x76543210)
<suprothunderbolt>
31:15 / / / unused
<suprothunderbolt>
so not sure why it's not 0x00003210
<suprothunderbolt>
if 4567 are unmappable.
<mripard>
suprothunderbolt: my understanding is that it can output either 8 channels in TDM (so over a single "lane") and there's some example of that in the timing diagram in the user manual?
<suprothunderbolt>
mripard, thanks for the reference to the timing diagram, I'll check it
<mripard>
ah, I have an older version here (1.0)
<mripard>
it might be that the old one is wrong
<mripard>
so we're both right :)
<mripard>
(and both versions are consistent)
<mripard>
there's several instances of the i2s controller
<mripard>
the one you were mentioning indeed seem to only be able to deal with 4 channels
<mripard>
and is the one going to the embedded audio codec
<mripard>
but there's also some generic purpose I2S controller with the digital bus going over some of the SoC pins
<mripard>
and those can deal with 8 channels
<mripard>
otherwise they have the same design
<suprothunderbolt>
oh okay, what's the registers for the 8 channel one? I'll then just have to work out why my other channels aren't working I was worried it was wrong
<suprothunderbolt>
the timing diagram mentions all 8 channels in TDM mode
<suprothunderbolt>
ahh page 637, my mistake. I saw there was 2 I2S channels but assumed they were the same.
<mripard>
yep :)
<suprothunderbolt>
mripard, thanks for the help! Now I'll attempt to work out why it isn't working... :) the first 4 channels are coming through fine and I've got it connected to this pin.
<suprothunderbolt>
thanks again
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<apritzel>
it's what I posted yesterday, on top of this in -next
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<BenG83>
ah ok, thanks for the heads up
<apritzel>
BenG83: the *mechanical* switches between SOPine and LTS have inverted semantic (the SOPine has a "push-pull" style switch), and that's why I think there is this inverter transistor on the Pine64-LTS
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<apritzel>
which makes the level on the GPIO pin the same, so that the SOPine and LTS stay compatible
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<apritzel>
that's at least my theory on this
<BenG83>
I was wondering about that, but could not find the card slot info quickly
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<palmer>
I'm just dropping in to say hi -- not sure if any of you guys have a D1 yet, but I am obviously pretty excited for it. LMK if there's anything I can do to help!
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<dlan>
palmer: re D1, I heard that they are busy validating.. but not ship yet, due to shortage of chips (for global tight silicon production capacity)
<palmer>
there was a twitter this morning about it shipping in May
<palmer>
let me see if I can dig it up, maybe I misread somethnig
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<vagrantc>
what shipping?
<[TheBug]>
can I ask something though, D1, why??
<[TheBug]>
I don't know I see the value of that board, but I am sure there is one there
<[TheBug]>
I mean is it supposed to be for a media box with all the VPU stuff, or is it supposed to be a low power IoT device.. its seems a bit confused
<palmer>
IMO it's just a proving ground for their RISC-V IP
<palmer>
I can't find the May date, so maybe I'm just wrong
<[TheBug]>
but essentially a A10 would have more mature support wouldn't it?
<[TheBug]>
and do most of those things ( okay not some of the video decode)
<[TheBug]>
ahh I see someone on CNX mentioned, "This is chip is optimized to build Amazon Echo type audio devices. "
<palmer>
ya, well, anything ARM based is going to have better software support than anything RISC-V based