rellla changed the topic of #linux-sunxi to: Allwinner/sunxi /development discussion - did you try looking at our wiki? https://linux-sunxi.org - Don't ask to ask. Just ask and wait! - https://github.com/linux-sunxi/ - Logs at http://irclog.whitequark.org/linux-sunxi - *only registered users can talk*
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<swiftgeek> > 1f3a:efe8 Allwinner Technology sunxi SoC OTG connector in FEL/flashing mode
<swiftgeek> after removing DRAM
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<swiftgeek> > AWUSBFEX soc=00001667(A33) 00000001 ver=0001 44 08 scratchpad=00007e00 00000000 00000000
<swiftgeek> i wonder if i can dump brom from fel alone :D
<smaeul> you can
<swiftgeek> sunxi-fel hex 0xFFFF0000 0x0
<swiftgeek> usb_bulk_recv() ERROR -8: Overflow
<swiftgeek> welp :D
<swiftgeek> had to restart :D
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<swiftgeek> sunxi-fel dump 0xFFFF0000 0x8000 > a33-brom-dump.bin ; that worked for me :D
<swiftgeek> i'm a bit curious about that lack of FEL strap / boot select pin, maybe i will look into it
<swiftgeek> it's pretty annoying to not have such option
<smaeul> A33 manual says: if you want to boot the system directly from USB, the UBOOT_SEL pin pulled up by internal 50K resistor in normal state can be set to low level
<swiftgeek> yeah and such pin does not exist in both reference schematics and datasheet
<smaeul> ah. you could check the BROM for references to 0x01c00024 (VER_REG) which is where the pin is usually exposed
<smaeul> although the register could exist without the physical pin
<swiftgeek> https://dpaste.com/B386N3CZL.txt I'm afraid I don't see that in there
<smaeul> try little endian :) the code is at 0xffff6d68
<swiftgeek> i don't see 0x2400c001 either in my dump
<swiftgeek> oh
<smaeul> also, thanks for the dump, I added it to https://github.com/smaeul/sunxi-blobs
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<swiftgeek> if BOOT_SEL_PAD_STA is indeed showing current status, i guess JTAG (boundary scan) could help with finding the pin
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<swiftgeek> though that's probably not implemented
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<swiftgeek> `watch -n1 sunxi-fel hex 0x01c00024 0x4` and pressing buttons didn't change anything
<suprothunderbolt> I'm still attempting to get this i2s stuff to work, I've tested 64 lclock and 32, just checking now to see if it actually looks different on the scope or not
<swiftgeek> H3 actually responds in real time
<swiftgeek> (decreased to -n0.1 )
<swiftgeek> that's neat
<swiftgeek> instead of wondering what works one can just query it directly
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<JoaoSchim> MoeIcenowy: yes i know. 2013 there about. Still very capable for what i need. What current SoC would you advise for next project ?
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<MoeIcenowy> got our old friend FEL mode on D1's RISC-V core
<MoeIcenowy> (but we need to make sunxi-fel support multiple CPU architectures
<ElBarto> MoeIcenowy: do you have access to a board ?
<MoeIcenowy> ElBarto: yes, a board is passed by AW to Pine64, then to me
<ElBarto> cool
<ElBarto> maybe when I'll get one u-boot part will be done and I'll just need to focus on FreeBSD then :)
<apritzel> ElBarto: don't hold your breath, though, there are only a very few boards in existence
<ElBarto> yeah I know, I'll probably get my beagle-v first anyway (and I'll have a lot to do on it)
<MoeIcenowy> ElBarto: is Beagle-V delayed?
<ElBarto> I don't think so, iirc most of us should receive it this month
<ElBarto> that was the latest news anyway
<apritzel> MoeIcenowy: so the FEL protocol itself is the same, we just need to prepare sunxi-fel to upload RISC-V code?
<MoeIcenowy> apritzel: yes
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<swiftgeek> Can I install single 16bit wide ram chip and have A33 work with it?
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<swiftgeek> i'm actually not sure how it even works with two chips
<swiftgeek> oh
<swiftgeek> it does not
<swiftgeek> reference schematics (and schematics of device i have here) assume that I have either single CS ram chip
<swiftgeek> err
<swiftgeek> *single dual /CS ram chip, or two chips with single /CS
<swiftgeek> so to have 2x 1GiB ram i would need to have either 4 /CS on SoC or twice the DQ lines
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<swiftgeek> ok looks like i found something that might fit if it was available https://www.digikey.at/htmldatasheets/production/1959024/0/0/1/MT41K1G16.pdf
<swiftgeek> somehow i can't find anything with single die/CS at capacity of 1GiB ;D
<swiftgeek> > Since DDR is an universal device. So you can test
<swiftgeek> lol :D
<swiftgeek> > 512M x 16bit 单片选
<swiftgeek> I guess that matches MT41K512M16
<swiftgeek> reading "A33 A23 DDR3 DDR3L全兼容模板使用注意事项.pdf" is hard without knowing the language lol
<swiftgeek> I guess it will work fine with single MT41K512M16, will be even a bit more optimal since it would use a single rank/cs, and configuration with two of such chips is completely untested
<swiftgeek> but if i can test single chip configuration first, that would be a much smaller issue to deal with
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