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<xobs> florent: Do you have any recommendations on how I can avoid double-naming? Should I have DCSR inherit from CSRStatus and CSRStorage? Or is there some way I can inhibit the name of the instantiated CSR?
<_florent_> xobs: i wanted to play a bit with your code to figure that out, i'm just finishing something and will look at that
<_florent_> xobs: the way you did it, it's difficult to improve the naming. You have a common Reg Module, but then switch inside it if it's readable/writable
<xobs> _florent_: I was mimicking how CSR does it. Is there a way you'd suggest doing it instead?
<_florent_> xobs: i think you should have some helpers functions outside of Reg to do the common processing on the fields
<_florent_> then maybe just have RegStorage be RegStorage(CSRStorage)
<_florent_> and do the processing of the field before the CSRStorage.__init__(self, ...)
<_florent_> and the reset logic insertion after
<xobs> Okay, I'll change my approach and do that then. Thanks for the advice!
<_florent_> and the same for RegStatus
<_florent_> this is just what i think, but this way, the naming will be similar to using regular CSRStatus/CSRStorage
<_florent_> and you will avoid having the:
<tpb> Title: Snippet | IRCCloud (at www.irccloud.com)
<_florent_> since it will be directly accessible
<xobs> Well, one thing I want to avoid is namespace collisions. For example, what if you want a field called "status"? Or "re"? That's one of the reasons behind the requirement that fields not begin with "_".
<_florent_> ok i see, maybe you could also do it with a specific __getattr__ (of otherwise prohibit the use of "status", "storage", "re", "we" in the fields as we are doing on streams: https://github.com/enjoy-digital/litex/blob/master/litex/soc/interconnect/stream.py#L33
<tpb> Title: litex/stream.py at master · enjoy-digital/litex · GitHub (at github.com)
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<xobs> I see you're right, florent, it really doesn't want to work that way. That's unfortunate.
<xobs> For example, the global `csrprefix` def appears to assume that all CSRs have a `.name` property, which means I can't do a `DCSR` with a `name` Field on it. Not unless I add it to a sub-property.
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<somlo> mithro: I'll take a look (as soon as finish waking up :)
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<_florent_> John_K: i don't have the right license right now so can't test the implementation, but i adapted your code to be closer to what is used on Numato Opsis:
<tpb> Title: litex-buildenv/base.py at master · timvideos/litex-buildenv · GitHub (at github.com)
<_florent_> in a first time, i would recommend using the exact same frequency we are using on opsis: 50MHz
<_florent_> you can find the ddram constraints of the opsis here: https://github.com/timvideos/litex-buildenv/blob/master/platforms/opsis.py#L184-L209
<tpb> Title: litex-buildenv/opsis.py at master · timvideos/litex-buildenv · GitHub (at github.com)
<mithro> _florent_: is https://github.com/ikwzm/udmabuf have any potential use with LiteX?
<tpb> Title: GitHub - ikwzm/udmabuf: User space mappable dma buffer device driver for Linux. (at github.com)
<john_k[m]> thanks _florent_ I'll look into it. For the toolchain, you need the "Windows 10" version of ISE 14.7 (Xilinx are really bad at versioning)
<john_k[m]> I'mI'm going to write up instructions for how to get the "Windows 10" version to work under Linux (at mithro's prodding) - it adds support for S6 LX100/LX150 devices and comes with a permanent license
<mithro> john_k[m]: that would be awesome!
<john_k[m]> :) it takes a lot of tools, going to see if I can optimize it a bit and and a shell script to transform it into something usable
<john_k[m]> florent
<john_k[m]> * florent it's close, https://hastebin.com/raw/orayudutom
<tpb> Title: Bash On Windows · timvideos/litex-buildenv Wiki · GitHub (at github.com)
<john_k[m]> I haven't, but I prefer to use Linux for FPGA development. Plus the "Windows 10" version of ISE is a Linux VM that runs on Windows anyway
<somlo> _florent_, mithro: PTAL @ https://github.com/enjoy-digital/litex/wiki/Soft-CPU and let me know if the rocket stuff looks about right, or if you think I missed anything
<tpb> Title: Soft CPU · enjoy-digital/litex Wiki · GitHub (at github.com)
<john_k[m]> that reads well somlo, was surpised that the FPU isn't enabled in the Linux config
<_florent_> john_k[m]: l55, you have p = 8, it should work with p=16
<_florent_> mithro: i'll look at udmabuf and compare to what we are doing in litepcie
<john_k[m]> _florent_: aha, trying that now (was attempting to change CPU back to 100MHz to see if that would fix it)
<john_k[m]> at some point, would like to pick your brain about the different styles of instantiating PLLs
<_florent_> john_k[m]: i would say the style you started implemented things is now recommended (using S6PLL)
<_florent_> but the thing is that getting DRAM working is already complicated on Spartan6, so that's better just using the code that is known to work on the Opsis for now
<john_k[m]> it does seem a bit neater, will have to play around with it a bit after we get this working
<john_k[m]> makes sense
<_florent_> once working, it will be easier to try the S6PLL with DDR3
<john_k[m]> DDR3?
<john_k[m]> (I presume you mean on a different board?)
<_florent_> isn't the panologic using a ddr3 memory?
<john_k[m]> DDR2
<somlo> john_k[m]: the FPU burns a lot of LUTs, and currently will not fit on an ecp5 45k FPGA (the versa-5g board from lattice)
<John_K> somlo: that makes sense
<_florent_> ah, then it's probably better to use the Atlys as a reference instead of the Opsis: https://github.com/timvideos/litex-buildenv/blob/master/targets/atlys/base.py
<tpb> Title: litex-buildenv/base.py at master · timvideos/litex-buildenv · GitHub (at github.com)
<John_K> _florent_: ah, hrm
<somlo> so I decided that the 'linux' variant will have the MMU only, and do floating point via software traps in the BBL
<_florent_> John_K: you should be able to almost copy/paste the CRG
<_florent_> you don't need the peripheral clock / encoder clock part
<somlo> I built a 'full' variant on the nexys4ddr (with Vivado) and it fits, and beats the pants off of the emulated variant in linpack :)
<_florent_> then also copy the sdram instance
<john_k[m]> _florent_: ok will try that if p=16 doesn't work
<_florent_> be sure that you have 1:2 in the sdram module, not 1:4
<john_k[m]> in general, is HalfRate or QuarterRate preferred? I'd want to think that QuarterRate would give more BW?
<_florent_> john_k[m]: sorry the code i adapted before won't work, i was thinking it was a DDR3
<john_k[m]> oh
<_florent_> ok Spartan6 it's pretty limited, we only validated DDR2 with HalfRate and DDR3 with QuarterRate
<_florent_> ok/on
<_florent_> john_k[m]: sorry i have to go, if it's not working, you can post your results here, i'll have a look later
<John_K> sounds good, thanks for all of your help _florent_
<John_K> all of this context is great to have
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