lekernel changed the topic of #m-labs to: Mixxeo, Migen, MiSoC & other M-Labs projects :: fka #milkymist :: Logs http://irclog.whitequark.org/m-labs
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<JewFro297> So, does Wishbone interconnect allow for data transfer from different clock domains?
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<sb0> JewFro297, wishbone itself no; but you can have two wishbone buses, one in each clock domain, and have some bridge core between the two
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<mumptai> is there actually a bus with built-in clock-domain crossing?
<larsc> depends on what you mean by built-in
<larsc> AXI works fine if you add a fifo on the bus for domain crossing
<larsc> or whatever else
<larsc> you want to use for domain crossing
<larsc> it's basically message based and the messages only ever travel in one direction
<larsc> so when you want to cross clock domains you can use your faviourite clock-domain crossing method
<larsc> so in a sense there is no built-in support for it, since it doesn't require anything special
<mumptai> mhmm, arbittration gotta be more tricky with it ;)
<larsc> it's super easy ;)
<mumptai> wasnÄ
<mumptai> wasn't it capable of out-of-order transfers?
* mumptai has to read overview & introduction again
<larsc> axi3 was, but this was dropped for axi4
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<mumptai> so, the default implementation is buffered cross-bar, with optional cd-crossing in the buffers?
<larsc> I don't think there is a default implementation
<larsc> but yea, that sounds about right for a typical implementation
<larsc> you don't need the buffers though if you don't care about throughput
<mumptai> you can always choose the buffer implementation, per port ;)
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<kristianpaul> ahmm, axi is amba, tought was something from opencores :|
<larsc> well it's royalty free and the specification is available
<mumptai> but no bfm and references?
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