#m-labs on 2014-02-13 — irc logs at freenode.irclog.whitequark.org

2013-12-11 12:34 lekernel changed the topic of #m-labs to: Mixxeo, Migen, MiSoC & other M-Labs projects :: fka #milkymist :: Logs http://irclog.whitequark.org/m-labs

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15:56 <davidc__> lekernel: interested in a mibuild platform for the lattice iCEcube2 toolchain + one of their demoboards? (does the low-power stuff they bought from siliconblue)

15:56 <lekernel> yes

15:58 <davidc__> lekernel: Ok; it seems to work at the moment. Once I have the platform + a bit more constraint work done (should be <+24h), I'll send to list

16:02 <ysionneau> :)

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20:50 <GitHub6> [NetBSD] fallen pushed 1 new commit to master: http://git.io/polvLg

20:50 <GitHub6> NetBSD/master cfb48e9 Yann Sionneau: Now using same kind of pmap like PPC BookE / MPC85xx...

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21:00 <bvernoux> hi

21:00 <ysionneau> hi

21:02 <bvernoux> Where can I see an example of what is generated with migen ?

21:02 <ysionneau> you can run it for instance

21:03 <ysionneau> you can have a look at a minimalistic example : http://jeffrey.co.in/blog/2014/01/d-flip-flop-using-migen/

21:03 <ysionneau> via print(verilog.convert(......)) you can get the verilog output

21:05 <bvernoux> ha thanks

21:05 <bvernoux> ysionneau: in fact i work on project daisho with mike ossmann and other members

21:06 <ysionneau> this: http://ossmann.blogspot.fr/2013/05/introducing-daisho.html ?

21:06 <bvernoux> yes

21:07 <ysionneau> it's kind of a logic analyser ?

21:07 <ysionneau> (I don't know daisho)

21:07 <bvernoux> not really

21:07 <bvernoux> a multipurpose base board to sniff/inject wired buse

21:08 <bvernoux> bus

21:08 <bvernoux> for HDMI, USB 3.0, Gigabit Eth ...

21:08 <ysionneau> ah, kind of like the "bus pirate"

21:08 <bvernoux> sniff => monitoring if you prefer

21:09 <bvernoux> ysionneau: at a lower layer than buspirate but same idea basically

21:09 <ysionneau> but more advanced

21:09 <ysionneau> ok :)

21:10 <bvernoux> i'm also waiting parallella board with zyn7020

21:10 <bvernoux> zynq7020

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21:16 <ysionneau> bvernoux: don't hesitate to use the mailing list as well for questions regarding Migen

21:17 <ysionneau> sometimes nobody is looking at IRC so the list is handy

21:17 <bvernoux> yes thanks

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21:51 <GitHub179> [misoc] sbourdeauducq pushed 2 new commits to master: http://git.io/ay3d2g

21:51 <GitHub179> misoc/master 88d4962 Sebastien Bourdeauducq: targets/mlabs_video: use outer video inputs

21:51 <GitHub179> misoc/master bdb47e7 Sebastien Bourdeauducq: dvisampler: replace parity with sof

21:52 <davidc__> bvernoux: I was talking with Ossman at TC:S; and IIRC we talked about migen then. Glad to see you guys are looking at it more

21:53 <bvernoux> davidc__: in fact it is because i have speak with Florent Kermarrec today

21:54 <davidc__> bvernoux: eh, in any case. Its definitely worth looking at.

21:58 <bvernoux> anyway good quality open source tool for FPGA are welcome

21:59 <bvernoux> especially good open source IP for DDR controller ...

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